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Results 21 - 23 of 23 for isF32 (0.04 sec)

  1. tensorflow/compiler/mlir/tensorflow/transforms/lower_tf.td

       (TF_ConstOp:$one (GetScalarOfType<1> $num_lower)),
       (TF_ConstOp:$neg_one (GetScalarOfType<-1> $num_lower)),
       (GetDimensionSize<-2>:$m $input, (IsI32 $num_lower)),
       (GetDimensionSize<-1>:$n $input, (IsI32 $num_upper)),
       (TF_SelectV2Op:$num_lower_or_m (TF_LessOp $num_lower, $zero),
                                      $m, $num_lower),
       (TF_SelectV2Op:$num_upper_or_n (TF_LessOp $num_upper, $zero),
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 04 13:30:42 UTC 2024
    - 24.7K bytes
    - Viewed (0)
  2. src/unicode/letter.go

    			return range_.Stride == 1 || (r-range_.Lo)%range_.Stride == 0
    		}
    		if r < range_.Lo {
    			hi = m
    		} else {
    			lo = m + 1
    		}
    	}
    	return false
    }
    
    // is32 reports whether r is in the sorted slice of 32-bit ranges.
    func is32(ranges []Range32, r uint32) bool {
    	if len(ranges) <= linearMax {
    		for i := range ranges {
    			range_ := &ranges[i]
    			if r < range_.Lo {
    				return false
    			}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 06 20:02:46 UTC 2023
    - 10K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/ppc64/obj9.go

    		switch {
    		case isS32 && p.From.Offset&0xFFFF == 0 && p.From.Offset != 0:
    			p.As = AADDIS
    			p.From.Offset >>= 16
    			p.Reg = REG_R0
    
    		case isU32 && p.From.Offset&0xFFFF == 0 && p.From.Offset != 0:
    			p.As = AORIS
    			p.From.Offset >>= 16
    			p.Reg = REG_R0
    
    		case isS32 || isU32 || isS34:
    			// The assembler can generate this opcode in 1 (on Power10) or 2 opcodes.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 18:17:17 UTC 2024
    - 40.8K bytes
    - Viewed (0)
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