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Results 11 - 20 of 76 for add32a (0.1 sec)
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tensorflow/compiler/mlir/tfrt/tests/sink_in_invariant_ops.mlir
// CHECK: [[handle:%.*]] = "tf.VarHandleOp"() // CHECK: "tf.ReadVariableOp"([[handle]]) %0 = "tf.ReadVariableOp"(%arg1) {device = "/device:CPU:0"} : (tensor<*x!tf_type.resource>) -> tensor<1x3xf32> %1 = "tf.AddV2"(%arg0, %0) {device = "/device:CPU:0"} : (tensor<1x3xf32>, tensor<1x3xf32>) -> tensor<1x3xf32> %2 = "tf.Identity"(%1) {device = "/device:CPU:0"} : (tensor<1x3xf32>) -> tensor<1x3xf32> func.return %2 : tensor<1x3xf32> }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 21K bytes - Viewed (0) -
src/runtime/pprof/proto_test.go
map1, map2 = fake, fake } return } func TestConvertCPUProfile(t *testing.T) { addr1, addr2, map1, map2 := testPCs(t) b := []uint64{ 3, 0, 500, // hz = 500 5, 0, 10, uint64(addr1 + 1), uint64(addr1 + 2), // 10 samples in addr1 5, 0, 40, uint64(addr2 + 1), uint64(addr2 + 2), // 40 samples in addr2 5, 0, 10, uint64(addr1 + 1), uint64(addr1 + 2), // 10 samples in addr1 }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jan 31 23:21:53 UTC 2024 - 17K bytes - Viewed (0) -
tensorflow/compiler/mlir/tfrt/tests/hoist_invariant_ops.mlir
// CHECK-NEXT: "tf.AddV2"({{.*}}, [[v]]) {device = "/CPU:0"} : (tensor<i32>, tensor<i32>) -> tensor<i32> // CHECK-NEXT: return %const = "tf.Const"() {device = "/CPU:0", value = dense<0> : tensor<i32>} : () -> tensor<i32> %x = "tf.AddV2"(%const, %const) {device = "/CPU:0"} : (tensor<i32>, tensor<i32>) -> tensor<i32> %r = "tf.AddV2"(%arg, %x) {device = "/CPU:0"} : (tensor<i32>, tensor<i32>) -> tensor<i32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Apr 01 23:54:14 UTC 2024 - 18.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/tests/prepare_lifting.mlir
// CHECK: %[[mul:.*]] = "tf.Mul"(%arg0, %[[CONST_0]]) : (tensor<*xf32>, tensor<2xf32>) -> tensor<*xf32> // CHECK: %[[add:.*]] = "tf.AddV2"(%[[mul]], %[[CONST]]) : (tensor<*xf32>, tensor<2xf32>) -> tensor<*xf32> // CHECK-NEXT: return %[[add]] : tensor<*xf32> // ----- func.func @not_decompose_batch_norm(%arg0: tensor<*xf32>) -> (tensor<*xf32>) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Feb 14 03:24:59 UTC 2024 - 33.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/lower-static-tensor-list.mlir
// CHECK-LABEL: func @otherVariantWhileBody // CHECK: [[CST:%.*]] = "tf.Const"() // CHECK-NEXT: [[ADD:%.*]] = "tf.AddV2"(%arg2, [[CST]]) // CHECK-NEXT: [[TENSOR_MAP_INSERT_RESULT:%.*]] = "tf.TensorMapInsert"(%arg3, %arg2, %arg2) // CHECK-NEXT: [[ADD_2:%.*]] = "tf.AddV2"(%arg0, [[CST]]) // CHECK-NEXT: return [[ADD_2]], %arg1, [[ADD]], [[TENSOR_MAP_INSERT_RESULT]]
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 39.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/update_control_dependencies.mlir
%add2, %add2_control = tf_executor.island(%add1_control) wraps "tf.Add"(%add1, %arg1) : (tensor<*xi32>, tensor<i32>) -> tensor<*xi32> %print, %print_control = tf_executor.island wraps "tf.Print"(%add2) {message = "add2 result"} : (tensor<*xi32>) -> tensor<*xi32> tf_executor.fetch %add1, %add2, %add2_control : tensor<*xi32>, tensor<*xi32>, !tf_executor.control }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Nov 03 18:12:49 UTC 2023 - 25.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/quantization/tensorflow/tests/fallback_to_flex_ops_default.mlir
%0 = "tf.Identity"(%cst) {device = ""} : (tensor<1xf32>) -> tensor<1xf32> %1 = "tf.AddV2"(%0, %cst_1) {device = ""} : (tensor<1xf32>, tensor<f32>) -> tensor<1xf32> %2 = "tf.Conv2DBackpropInput"(%arg0, %arg1, %arg2) {strides = [1, 2, 2, 1], padding="SAME", dilations=[1, 1, 1, 1]}: (tensor<4xi32>, tensor<3x3x1x32xf32>, tensor<15x14x14x32xf32>) -> tensor<15x28x28x1xf32> %3 = "tf.AddV2"(%2, %1): (tensor<15x28x28x1xf32>, tensor<1xf32>) -> tensor<15x28x28x1xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 13.4K bytes - Viewed (0) -
tensorflow/compiler/jit/xla_launch_util_test.cc
*literal2, xla::LiteralUtil::CreateR2<int32_t>({{3, 4}}))); } TEST_F(PjRtExecutionUtilTest, PopulateCtxOutputs) { XlaOpRegistry::RegisterCompilationKernels(); TF_EXPECT_OK(NodeDefBuilder("AddV2", "AddV2") .Input(FakeInput(DT_INT32)) .Input(FakeInput(DT_INT32)) .Attr("T", DT_INT32) .Device("/job:localhost/replica:0/task:0/device:XLA_CPU:0")
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Feb 21 09:53:30 UTC 2024 - 28.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/tests/lift_hashtable_ops_as_args.mlir
%3 = "tf.LookupTableSizeV2"(%1) {device = ""} : (tensor<!tf_type.resource>) -> tensor<i64> %4 = "tf.AddV2"(%2, %3) {device = ""} : (tensor<i64>, tensor<i64>) -> tensor<i64> %5 = "tf.LookupTableFindV2"(%0, %arg0, %cst) {device = ""} : (tensor<!tf_type.resource>, tensor<?x!tf_type.string>, tensor<i64>) -> tensor<*xi64> %6 = "tf.AddV2"(%5, %4) {device = ""} : (tensor<*xi64>, tensor<i64>) -> tensor<*xi64> return %6 : tensor<*xi64> }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Mar 15 05:41:44 UTC 2024 - 13.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/split_into_island_per_op.mlir
%island1:3 = tf_executor.island { %add1 = "tf.Add"(%arg0, %arg1) : (tensor<*xi32>, tensor<i32>) -> tensor<*xi32> %add2 = "tf.Add"(%add1, %arg1) : (tensor<*xi32>, tensor<i32>) -> tensor<*xi32> %res = "tf.Print"(%add2) { message = "add result" } : (tensor<*xi32>) -> (tensor<*xi32>) tf_executor.yield %add1, %add2 : tensor<*xi32>, tensor<*xi32> } tf_executor.fetch %island1#0, %island1#1 : tensor<*xi32>, tensor<*xi32> }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 20.2K bytes - Viewed (0)