name: header-http-echo
spec:
  parentRefs:
    - name: acme-gw
  rules:
    - matches:
        - path:
            type: PathPrefix
            value: /add-a-request-header
      filters:
        - type: RequestHeaderModifier
          requestHeaderModifier:
            add:
              - name: my-header-name
                value: my-header-value
      backendRefs:
        - name: echo

  %0 = "tfl.custom"(%arg0, %arg0) {custom_code = "stablehlo.add", custom_option = #tfl<const_bytes : "0x00000100002401">} : (tensor<2xi32>, tensor<2xi32>) -> tensor<2xi32>
  func.return %0 : tensor<2xi32>
}
}

// CHECK:       module {
// CHECK-NEXT:  func @main(%arg0: tensor<2xi32>) -> tensor<2xi32> attributes {tf.entry_function = {inputs = "arg0", outputs = "tfl.custom1"}} {
// CHECK-NEXT:    %0 = stablehlo.add %arg0, %arg0 : tensor<2xi32>

		fallthrough

	case FCMP, FCMPE:
		if _, ok := inst.Args[1].(Imm); ok {
			args[1] = "$(0.0)"
		}
		fallthrough

	case FADD, FSUB, FMUL, FNMUL, FDIV, FMAX, FMIN, FMAXNM, FMINNM, FCSEL, FMADD, FMSUB, FNMADD, FNMSUB:
		if strings.HasSuffix(op, "MADD") || strings.HasSuffix(op, "MSUB") {
			args[2], args[3] = args[3], args[2]
		}
		if r, ok := inst.Args[0].(Reg); ok {
			rno := uint16(r)

	{AADD, C_BITCON, C_RSP, C_NONE, C_RSP, C_NONE, 62, 8, 0, 0, 0},
	{AADD, C_BITCON, C_NONE, C_NONE, C_RSP, C_NONE, 62, 8, 0, 0, 0},
	{ACMP, C_BITCON, C_RSP, C_NONE, C_NONE, C_NONE, 62, 8, 0, 0, 0},
	{AADD, C_ADDCON2, C_RSP, C_NONE, C_RSP, C_NONE, 48, 8, 0, NOTUSETMP, 0},
	{AADD, C_ADDCON2, C_NONE, C_NONE, C_RSP, C_NONE, 48, 8, 0, NOTUSETMP, 0},
	{AADD, C_MOVCON2, C_RSP, C_NONE, C_RSP, C_NONE, 13, 12, 0, 0, 0},

					// Restore frame pointer.
					// ADD $framesize-8, RSP, R29
					p.As = AADD
					p.From.Type = obj.TYPE_CONST
					p.From.Offset = int64(c.autosize) - 8
					p.Reg = REGSP
					p.To.Type = obj.TYPE_REG
					p.To.Reg = REGFP

					// Pop stack frame.
					// ADD $framesize, RSP, RSP
					p = obj.Appendp(p, c.newprog)
					p.As = AADD
					p.From.Type = obj.TYPE_CONST

	// FADD <Sd>, <Sn>, <Sm>
	{0xffe0fc00, 0x1e202800, FADD, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
	// FADD <Dd>, <Dn>, <Dm>
	{0xffe0fc00, 0x1e602800, FADD, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
	// FADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t>

(MADD a (MOVDconst [-1]) x) => (SUB a x)
(MADD a (MOVDconst [0]) _) => a
(MADD a (MOVDconst [1]) x) => (ADD a x)
(MADD a (MOVDconst [c]) x) && isPowerOfTwo64(c) => (ADDshiftLL a x [log64(c)])
(MADD a (MOVDconst [c]) x) && isPowerOfTwo64(c-1) && c>=3 => (ADD a (ADDshiftLL <x.Type> x x [log64(c-1)]))
(MADD a (MOVDconst [c]) x) && isPowerOfTwo64(c+1) && c>=7 => (SUB a (SUBshiftLL <x.Type> x x [log64(c+1)]))

	BYTE	$0x00
	BYTE	$0x19
	BGE	L16
	BVS	L16
	WFCEDBS	V2, V2, V2
	BVS	LEXITTAGexp
	MOVD	$·expxaddexp<>+0(SB), R1
	FMOVD	72(R5), F6
	FMOVD	0(R1), F2
	WFMSDB	V0, V6, V2, V6
	FMOVD	64(R5), F4
	FADD	F6, F2
	FMOVD	56(R5), F1
	FMADD	F4, F2, F0
	FMOVD	48(R5), F3
	WFMADB	V2, V1, V0, V2
	FMOVD	40(R5), F1
	FMOVD	32(R5), F4
	FMUL	F0, F0
	WFMADB	V2, V4, V1, V4
	LGDR	F6, R1
	FMOVD	24(R5), F1

		mips.ACMPGTF, mips.ACMPGTD:
		return true
	}
	return false
}

// IsMIPSMUL reports whether the op (as defined by an mips.A* constant) is
// one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling.
func IsMIPSMUL(op obj.As) bool {
	switch op {
	case mips.AMUL, mips.AMULU, mips.AMULV, mips.AMULVU,
		mips.ADIV, mips.ADIVU, mips.ADIVV, mips.ADIVVU,

			}
			if rela != 0 {
				rAdd = int64(add)
			} else {
				// load addend from image
				if rSize == 4 {
					rAdd = int64(e.Uint32(sect.base[rOff:]))
				} else if rSize == 8 {
					rAdd = int64(e.Uint64(sect.base[rOff:]))
				} else {
					return errorf("invalid rela size %d", rSize)
				}
			}

			if addendSize == 2 {
				rAdd = int64(int16(rAdd))
			}
			if addendSize == 4 {