},
		},
		{
			file: "escaping.dot",
			nodes: []*dotVertex{
				NewDOTVertex(makeNode(ref1, withOwners(ref2))),
				NewDOTVertex(makeNode(ref2)),
			},
			edges: []dotEdge{
				{F: types.UID(ref1.UID), T: types.UID(ref2.UID)},
			},
		},
	}

	for _, tc := range testcases {
		t.Run(tc.file, func(t *testing.T) {

	C_SACON    /* $n(REG) where n <= int16 */
	C_LACON    /* $n(REG) where n <= int32 */
	C_DACON    /* $n(REG) where n <= int64 */
	C_BRA      /* A short offset argument to a branching instruction */
	C_BRAPIC   /* Like C_BRA, but requires an extra NOP for potential TOC restore by the linker. */
	C_ZOREG    /* An $0+reg memory op */
	C_SOREG    /* An $n+reg memory arg where n is a 16 bit signed offset */

func (c *sigctxt) r5() uint64   { return c.regs().gregs[5] }
func (c *sigctxt) r6() uint64   { return c.regs().gregs[6] }
func (c *sigctxt) r7() uint64   { return c.regs().gregs[7] }
func (c *sigctxt) r8() uint64   { return c.regs().gregs[8] }
func (c *sigctxt) r9() uint64   { return c.regs().gregs[9] }
func (c *sigctxt) r10() uint64  { return c.regs().gregs[10] }
func (c *sigctxt) r11() uint64  { return c.regs().gregs[11] }

h� �M��j�JF��RR�I�33E�&$0��J�_�~�d�M- �$�Z� ��Z U�в�P�有�0X�S%�b�RdŁ� f� 5�%i��֤�X*�i�3�C��1�5�6a�ȵ�h ��c+�)�+������QNҿ�d��K�(�+�M3�5V����*Q�9U��H�m�Џ�����'� ���m���O�"g� �ӊO��j3%j�&d>��>:���O�����2O�Q]2����w�����W� 7�jy�0>��^|XeG2���j�����Pcc�J���ʹ����CF�?Xk̹�fm�]��6a�M�FK m\ھ��s|�Z���fG�U�dWj���x�R6[ ��2�&���f���+���.I��S �yݭ��~)���\mE��Q�2�������m�Z��L�;P�l"f�jk��f�jk��H#Ob�ĕ:��Ë��\9�:TV��U�9��CV�2�LYiY�9T�1FZU�9�аЙeK ƥ0�&YJ���1K�*a����p�� 
͚͙�2�Bsf�fp�L�...

}

// PtraceSetRegsMips sets the registers used by mips binaries.
func PtraceSetRegsMips(pid int, regs *PtraceRegsMips) error {
	return ptracePtr(PTRACE_SETREGS, pid, 0, unsafe.Pointer(regs))
}

// PtraceRegsMips64 is the registers used by mips64 binaries.
type PtraceRegsMips64 struct {
	Regs     [32]uint64
	Lo       uint64
	Hi       uint64
	Epc      uint64
	Badvaddr uint64
	Status   uint64

        Restriction res1 = i1.next();
        Restriction res2 = i2.next();

        boolean done = false;
        while (!done) {
            if (res1.getLowerBound() == null
                    || res2.getUpperBound() == null
                    || res1.getLowerBound().compareTo(res2.getUpperBound()) <= 0) {
                if (res1.getUpperBound() == null
                        || res2.getLowerBound() == null

}

// PtraceSetRegSetArm64 sets the registers used by arm64 binaries.
func PtraceSetRegSetArm64(pid, addr int, regs *PtraceRegsArm64) error {
	iovec := Iovec{(*byte)(unsafe.Pointer(regs)), uint64(unsafe.Sizeof(*regs))}
	return ptracePtr(PTRACE_SETREGSET, pid, uintptr(addr), unsafe.Pointer(&iovec))

		{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true},   // arg0 * arg1
		{name: "NMULF", argLength: 2, reg: fp21, asm: "NMULF", commutative: true}, // -(arg0 * arg1)
		{name: "NMULD", argLength: 2, reg: fp21, asm: "NMULD", commutative: true}, // -(arg0 * arg1)
		{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                      // arg0 / arg1

	switch aop {
	default:
		return nil

	case arg_Da:
		return D0 + Reg((x>>10)&(1<<5-1))

	case arg_Dd:
		return D0 + Reg(x&(1<<5-1))

	case arg_Dm:
		return D0 + Reg((x>>16)&(1<<5-1))

	case arg_Dn:
		return D0 + Reg((x>>5)&(1<<5-1))

	case arg_Hd:
		return H0 + Reg(x&(1<<5-1))

	case arg_Hn:
		return H0 + Reg((x>>5)&(1<<5-1))

	case arg_IAddSub:
		imm12 := (x >> 10) & (1<<12 - 1)

		{name: "FMOVDfpgp", argLength: 1, reg: fpgp, asm: "FMOVD"}, // move float64 to int64 (no conversion)
		{name: "FMOVSgpfp", argLength: 1, reg: gpfp, asm: "FMOVS"}, // move 32bits from int to float reg (no conversion)
		{name: "FMOVSfpgp", argLength: 1, reg: fpgp, asm: "FMOVS"}, // move 32bits from float to int reg, zero extend (no conversion)

		// conversions