if len(operands) == 0 && len(items) == 0 {
				if p.arch.InFamily(sys.ARM, sys.ARM64, sys.AMD64, sys.I386, sys.Loong64, sys.RISCV64) && tok == '.' {
					// Suffixes: ARM conditionals, Loong64 vector instructions, RISCV rounding mode or x86 modifiers.
					tok = p.nextToken()
					str := p.lex.Text()
					if tok != scanner.Ident {
						p.errorf("instruction suffix expected identifier, found %s", str)
					}
					cond = cond + "." + str

	VPEXTRW $127, X20, (SP)(AX*2)     // 62e37d081524447f or 62e3fd081524447f
	// EVEX: embedded zeroing.
	VADDPD.Z X30, X1, K7, X0  // 6291f58f58c6
	VMAXPD.Z (AX), Z2, K1, Z1 // 62f1edc95f08
	// EVEX: embedded rounding.
	VADDPD.RU_SAE Z3, Z2, K1, Z1   // 62f1ed5958cb
	VADDPD.RD_SAE Z3, Z2, K1, Z1   // 62f1ed3958cb
	VADDPD.RZ_SAE Z3, Z2, K1, Z1   // 62f1ed7958cb
	VADDPD.RN_SAE Z3, Z2, K1, Z1   // 62f1ed1958cb

	VASUBVV		V1, V2, V3			// d7a1202e
	VASUBVV		V1, V2, V0, V3			// d7a1202c
	VASUBVX		X10, V2, V3			// d761252e
	VASUBVX		X10, V2, V0, V3			// d761252c

	// 31.12.3: Vector Single-Width Fractional Multiply with Rounding and Saturation
	VSMULVV		V1, V2, V3			// d781209e
	VSMULVV		V1, V2, V0, V3			// d781209c
	VSMULVX		X10, V2, V3			// d741259e
	VSMULVX		X10, V2, V0, V3			// d741259c

				}
			}
		})
	}
}

// Benchmarks for ObjectLayer.PutObjectPart().
// The intent is to benchmark PutObjectPart for various sizes ranging from few bytes to 100MB.
// Also each of these Benchmarks are run both Erasure and FS backends.

// BenchmarkPutObjectPart5MbFS - Benchmark FS.PutObjectPart() for object size of 5MB.