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Results 31 - 40 of 95 for vmov (0.04 sec)

  1. src/cmd/internal/obj/s390x/anames.go

    	"VMLEB",
    	"VMLEH",
    	"VMLEF",
    	"VMLH",
    	"VMLHB",
    	"VMLHH",
    	"VMLHF",
    	"VMLO",
    	"VMLOB",
    	"VMLOH",
    	"VMLOF",
    	"VML",
    	"VMLB",
    	"VMLHW",
    	"VMLF",
    	"VMO",
    	"VMOB",
    	"VMOH",
    	"VMOF",
    	"VNO",
    	"VNOT",
    	"VO",
    	"VPK",
    	"VPKH",
    	"VPKF",
    	"VPKG",
    	"VPKLS",
    	"VPKLSH",
    	"VPKLSF",
    	"VPKLSG",
    	"VPKLSHS",
    	"VPKLSFS",
    	"VPKLSGS",
    	"VPKS",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Sep 05 16:41:03 UTC 2023
    - 7.1K bytes
    - Viewed (0)
  2. src/runtime/memclr_mips64x.s

    msa_large_loop:
    	VMOVB	W0, (R1)
    	VMOVB	W0, 16(R1)
    	VMOVB	W0, 32(R1)
    	VMOVB	W0, 48(R1)
    	VMOVB	W0, 64(R1)
    	VMOVB	W0, 80(R1)
    	VMOVB	W0, 96(R1)
    	VMOVB	W0, 112(R1)
    
    	ADDVU	$128, R1
    	SGTU	R6, R1, R3
    	BNE	R3, R0, msa_large_loop
    	BEQ	R5, R0, done
    	VMOVB	W0, -128(R4)
    	VMOVB	W0, -112(R4)
    	VMOVB	W0, -96(R4)
    	VMOVB	W0, -80(R4)
    	VMOVB	W0, -64(R4)
    	VMOVB	W0, -48(R4)
    	VMOVB	W0, -32(R4)
    	VMOVB	W0, -16(R4)
    	JMP	done
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sat Nov 06 10:24:44 UTC 2021
    - 1.7K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/AMD64.rules

    // rotate by constants
    (ROLQ x (MOV(Q|L)const [c])) => (ROLQconst [int8(c&63)] x)
    (ROLL x (MOV(Q|L)const [c])) => (ROLLconst [int8(c&31)] x)
    (ROLW x (MOV(Q|L)const [c])) => (ROLWconst [int8(c&15)] x)
    (ROLB x (MOV(Q|L)const [c])) => (ROLBconst [int8(c&7) ] x)
    
    (RORQ x (MOV(Q|L)const [c])) => (ROLQconst [int8((-c)&63)] x)
    (RORL x (MOV(Q|L)const [c])) => (ROLLconst [int8((-c)&31)] x)
    (RORW x (MOV(Q|L)const [c])) => (ROLWconst [int8((-c)&15)] x)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 93.9K bytes
    - Viewed (0)
  4. cmd/xl-storage-format-v2_test.go

    			// Mutate signature, non strict
    			vMod := make([][]xlMetaV2ShallowVersion, 0, len(vers))
    			for i, ver := range vers {
    				newVers := make([]xlMetaV2ShallowVersion, 0, len(ver))
    				for _, v := range ver {
    					v.header.Signature = [4]byte{byte(i + 10), 0, 0, 0}
    					newVers = append(newVers, v)
    				}
    				vMod = append(vMod, newVers)
    			}
    			merged := mergeXLV2Versions(i, false, 0, vMod...)
    			if len(merged) == 0 {
    Registered: Sun Jun 16 00:44:34 UTC 2024
    - Last Modified: Fri Mar 08 17:50:48 UTC 2024
    - 36.4K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/S390X.rules

    (MOV(B|BZ)reg e:(MOVWreg x)) && clobberIfDead(e) => (MOV(B|BZ)reg x)
    (MOV(H|HZ)reg e:(MOVHreg x)) && clobberIfDead(e) => (MOV(H|HZ)reg x)
    (MOV(H|HZ)reg e:(MOVWreg x)) && clobberIfDead(e) => (MOV(H|HZ)reg x)
    (MOV(W|WZ)reg e:(MOVWreg x)) && clobberIfDead(e) => (MOV(W|WZ)reg x)
    
    // Bypass redundant zero extensions.
    (MOV(B|BZ)reg e:(MOVBZreg x)) && clobberIfDead(e) => (MOV(B|BZ)reg x)
    (MOV(B|BZ)reg e:(MOVHZreg x)) && clobberIfDead(e) => (MOV(B|BZ)reg x)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 74.3K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/riscv64/ggen.go

    	// ADD	$(off), SP, T0
    	// ADD	$(cnt), T0, T1
    	// loop:
    	// 	MOV	ZERO, (T0)
    	// 	ADD	$Widthptr, T0
    	//	BNE	T0, T1, loop
    	p = pp.Append(p, riscv.AADD, obj.TYPE_CONST, 0, off, obj.TYPE_REG, riscv.REG_T0, 0)
    	p.Reg = riscv.REG_SP
    	p = pp.Append(p, riscv.AADD, obj.TYPE_CONST, 0, cnt, obj.TYPE_REG, riscv.REG_T1, 0)
    	p.Reg = riscv.REG_T0
    	p = pp.Append(p, riscv.AMOV, obj.TYPE_REG, riscv.REG_ZERO, 0, obj.TYPE_MEM, riscv.REG_T0, 0)
    	loop := p
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 19 15:59:22 UTC 2022
    - 1.8K bytes
    - Viewed (0)
  7. src/runtime/asm_riscv64.s

    	// X11 already saved (A1)
    	MOV	X12, 6*8(X2)
    	MOV	X13, 7*8(X2)
    	MOV	X14, 8*8(X2)
    	MOV	X15, 9*8(X2)
    	MOV	X16, 10*8(X2)
    	MOV	X17, 11*8(X2)
    	MOV	X18, 12*8(X2)
    	MOV	X19, 13*8(X2)
    	MOV	X20, 14*8(X2)
    	MOV	X21, 15*8(X2)
    	MOV	X22, 16*8(X2)
    	MOV	X23, 17*8(X2)
    	MOV	X24, 18*8(X2)
    	MOV	X25, 19*8(X2)
    	MOV	X26, 20*8(X2)
    	// X27 is g.
    	MOV	X28, 21*8(X2)
    	MOV	X29, 22*8(X2)
    	MOV	X30, 23*8(X2)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Nov 09 13:57:06 UTC 2023
    - 27K bytes
    - Viewed (0)
  8. src/runtime/rt0_freebsd_riscv64.s

    	MOV	$0x800000, A0                     // stacksize = 8192KB
    	MOV	$_rt0_riscv64_freebsd_lib_go(SB), A1
    	MOV	A0, 8(X2)
    	MOV	A1, 16(X2)
    	MOV	$runtime·newosproc0(SB), T0
    	JALR	RA, T0
    
    restore:
    	// Restore callee-save registers, along with X1 (LR).
    	MOV	(8*3)(X2), X1
    	MOV	(8*4)(X2), X8
    	MOV	(8*5)(X2), X9
    	MOV	(8*6)(X2), X18
    	MOV	(8*7)(X2), X19
    	MOV	(8*8)(X2), X20
    	MOV	(8*9)(X2), X21
    	MOV	(8*10)(X2), X22
    	MOV	(8*11)(X2), X23
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Sep 28 03:17:13 UTC 2022
    - 2.7K bytes
    - Viewed (0)
  9. src/runtime/memmove_riscv64.s

    	BNEZ	X5, f_align
    
    f_loop_check:
    	MOV	$16, X9
    	BLT	X12, X9, f_loop8_check
    	MOV	$32, X9
    	BLT	X12, X9, f_loop16_check
    	MOV	$64, X9
    	BLT	X12, X9, f_loop32_check
    f_loop64:
    	MOV	0(X11), X14
    	MOV	8(X11), X15
    	MOV	16(X11), X16
    	MOV	24(X11), X17
    	MOV	32(X11), X18
    	MOV	40(X11), X19
    	MOV	48(X11), X20
    	MOV	56(X11), X21
    	MOV	X14, 0(X10)
    	MOV	X15, 8(X10)
    	MOV	X16, 16(X10)
    	MOV	X17, 24(X10)
    	MOV	X18, 32(X10)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Nov 09 13:57:06 UTC 2023
    - 5.5K bytes
    - Viewed (0)
  10. src/internal/runtime/syscall/asm_linux_riscv64.s

    // err | A2          | part of A0
    TEXT ·Syscall6<ABIInternal>(SB),NOSPLIT,$0-80
    	MOV	A0, A7
    	MOV	A1, A0
    	MOV	A2, A1
    	MOV	A3, A2
    	MOV	A4, A3
    	MOV	A5, A4
    	MOV	A6, A5
    	ECALL
    	MOV	$-4096, T0
    	BLTU	T0, A0, err
    	// r1 already in A0
    	// r2 already in A1
    	MOV	ZERO, A2 // errno
    	RET
    err:
    	SUB	A0, ZERO, A2 // errno
    	MOV	$-1, A0	     // r1
    	MOV	ZERO, A1     // r2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Feb 21 21:28:32 UTC 2024
    - 969 bytes
    - Viewed (0)
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