// alignment requirements.
	ANDCC	$PAGE_OFFSET, R8, R6	// &sX & PAGE_OFFSET
	ANDCC	$PAGE_OFFSET, R4, R9
	SUBC	R5, $8, R12		// 8-len
	SLD	$3, R12, R14		// (8-len)*8
	CMPU	R6, R12, CR1		// Enough bytes lower in the page to load lower?
	CMPU	R9, R12, CR0
	SUB	R12, R8, R6		// compute lower load address
	SUB	R12, R4, R9
	ISEL	CR1LT, R8, R6, R8	// R8 = R6 < 0 ? R8 (&s1) : R6 (&s1 - (8-len))
	ISEL	CR0LT, R4, R9, R4	// Similar for s2

	RLWNM $3, R4, $29, $31, R6      // 54861f7e
	RLWNM $0, R4, $29, $31, R6      // 5486077e
	RLWNM R0, R4, $29, $31, R6      // 5c86077e
	RLWNM R3, R4, $7, R6            // 5c861f7e
	RLWNM R3, R4, $29, $31, R6      // 5c861f7e
	RLWNMCC $3, R4, $7, R6          // 54861f7f
	RLWNMCC $3, R4, $29, $31, R6    // 54861f7f
	RLWNMCC R3, R4, $7, R6          // 5c861f7f
	RLWNMCC R3, R4, $29, $31, R6    // 5c861f7f
	RLDMI $0, R4, $7, R6            // 7886076c

TEXT ·addMulVVW1024(SB), $0-32
	MOVD	$4, R6 // R6 = z_len/4
	JMP		addMulVVWx<>(SB)

// func addMulVVW1536(z, x *uint, y uint) (c uint)
TEXT ·addMulVVW1536(SB), $0-32
	MOVD	$6, R6 // R6 = z_len/4
	JMP		addMulVVWx<>(SB)

// func addMulVVW2048(z, x *uint, y uint) (c uint)
TEXT ·addMulVVW2048(SB), $0-32
	MOVD	$8, R6 // R6 = z_len/4
	JMP		addMulVVWx<>(SB)

// a1  | R5          | R4
// a2  | R6          | R5
// a3  | R7          | R6
// a4  | R8          | R7
// a5  | R9          | R8
// a6  | R10         | R9
//
// r1  | R4          | R4
// r2  | R5          | R5
// err | R6          | part of R4
TEXT ·Syscall6<ABIInternal>(SB),NOSPLIT,$0-80
	MOVV	R4, R11  // syscall entry
	MOVV	R5, R4
	MOVV	R6, R5
	MOVV	R7, R6
	MOVV	R8, R7
	MOVV	R9, R8
	MOVV	R10, R9

	LMG  0(R8), R5, R6
	MOVD $0, 0(R9)          // R9 address of SAVSTACK_ASYNC
	LE_CALL                 // balr R7, R6 (return #1)
	NOPH
	MOVD R3, ret+32(FP)
	CMP  R3, $-1            // compare result to -1
	BNE  done

	// retrieve errno and errno2
	MOVD  zosLibVec<>(SB), R8
	ADD   $(__errno), R8
	LMG   0(R8), R5, R6
	LE_CALL                   // balr R7, R6 __errno (return #3)
	NOPH

	ENDIAN_MOVE(16,R6,M04,M15)
	ENDIAN_MOVE(20,R6,M05,M15)
	ENDIAN_MOVE(24,R6,M06,M15)
	ENDIAN_MOVE(28,R6,M07,M15)

	ROUND1(R22,R3,R4,R5,M04,0xf57c0faf, 7);
	ROUND1(R5,R22,R3,R4,M05,0x4787c62a,12);
	ROUND1(R4,R5,R22,R3,M06,0xa8304613,17);
	ROUND1(R3,R4,R5,R22,M07,0xfd469501,22);

	ENDIAN_MOVE(32,R6,M08,M15)
	ENDIAN_MOVE(36,R6,M09,M15)
	ENDIAN_MOVE(40,R6,M10,M15)
	ENDIAN_MOVE(44,R6,M11,M15)

			},
			outputs: []outputInfo{
				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "MULA",
		argLen: 3,
		asm:    arm.AMULA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14

// SRL
	SRL	$0, R5, R6           // 0560a0e1
	SRL	$1, R5, R6           // a560a0e1
	SRL	$14, R5, R6          // 2567a0e1
	SRL	$15, R5, R6          // a567a0e1
	SRL	$30, R5, R6          // 256fa0e1
	SRL	$31, R5, R6          // a56fa0e1
	SRL	$32, R5, R6          // 2560a0e1
	SRL.S	$14, R5, R6          // 2567b0e1
	SRL.S	$15, R5, R6          // a567b0e1
	SRL.S	$30, R5, R6          // 256fb0e1

	MOVD	g_m(g), R6		//m

	MOVD	runtime·vdsoClockgettimeSym(SB), R9	// Check for VDSO availability
	CMPBEQ	R9, $0, fallback

	MOVD	m_vdsoPC(R6), R4
	MOVD	R4, 16(R15)
	MOVD	m_vdsoSP(R6), R4
	MOVD	R4, 24(R15)

	MOVD	R14, R8 		// Backup return address
	MOVD	$sec+0(FP), R4 	// return parameter caller

	MOVD	R8, m_vdsoPC(R6)
	MOVD	R4, m_vdsoSP(R6)

	MOVD	m_curg(R6), R5
	CMP		g, R5

	MOVD	savedm-8(SP), R6
	CMPBNE	R6, $0, droppedm

	// Skip dropm to reuse it in the next call, when a pthread key has been created.
	MOVD	_cgo_pthread_key_created(SB), R6
	// It means cgo is disabled when _cgo_pthread_key_created is a nil pointer, need dropm.
	CMPBEQ	R6, $0, dropm
	MOVD	(R6), R6
	CMPBNE	R6, $0, droppedm

dropm:
	MOVD	$runtime·dropm(SB), R3
	BL	(R3)