case APOPW, APOPL, APOPQ,
		ALEAL, ALEAQ,
		AIMUL3W, AIMUL3L, AIMUL3Q,
		APEXTRB, APEXTRW, APEXTRD, APEXTRQ, AVPEXTRB, AVPEXTRW, AVPEXTRD, AVPEXTRQ, AEXTRACTPS,
		ABSFW, ABSFL, ABSFQ, ABSRW, ABSRL, ABSRQ, APOPCNTW, APOPCNTL, APOPCNTQ, ALZCNTW, ALZCNTL, ALZCNTQ,
		ASHLXL, ASHLXQ, ASHRXL, ASHRXQ, ASARXL, ASARXQ:
		// These instructions are pure writes to To. They don't use its old value.
		m &^= readTo
	case AXORL, AXORQ:

(Bswap(64|32) ...) => (BSWAP(Q|L) ...)
(Bswap16 x) => (ROLWconst [8] x)

(PopCount(64|32) ...) => (POPCNT(Q|L) ...)
(PopCount16 x) => (POPCNTL (MOVWQZX <typ.UInt32> x))
(PopCount8 x) => (POPCNTL (MOVBQZX <typ.UInt32> x))

(Sqrt ...) => (SQRTSD ...)
(Sqrt32 ...) => (SQRTSS ...)

(RoundToEven x) => (ROUNDSD [0] x)
(Floor x)       => (ROUNDSD [1] x)

	/*6467*/ uint16(xCondPrefix), 1,
	0xF3, 6471,
	/*6471*/ uint16(xCondDataSize), 6475, 6481, 0,
	/*6475*/ uint16(xSetOp), uint16(POPCNT),
	/*6477*/ uint16(xReadSlashR),
	/*6478*/ uint16(xArgR16),
	/*6479*/ uint16(xArgRM16),
	/*6480*/ uint16(xMatch),
	/*6481*/ uint16(xSetOp), uint16(POPCNT),
	/*6483*/ uint16(xReadSlashR),
	/*6484*/ uint16(xArgR32),
	/*6485*/ uint16(xArgRM32),
	/*6486*/ uint16(xMatch),

				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "POPCNTW",
		argLen: 1,
		asm:    ppc64.APOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},

    auto output_type = op.getType().clone(
        rewriter.getIntegerType(/*width=*/8, /*isSigned=*/false));
    auto pop_cnt = rewriter.create<TF::PopulationCountOp>(
        op.getLoc(), output_type, op.getOperand());
    auto cast_or_pop_cnt =
        rewriter.createOrFold<TF::CastOp>(op.getLoc(), op.getType(), pop_cnt);
    rewriter.replaceOp(op, {cast_or_pop_cnt});
    return success();
  }
};

// Define a list of AMD64 microarchitecture level features
// https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels

                     // SSE3     SSSE3    CMPXCHNG16 SSE4.1    SSE4.2    POPCNT
#define V2_FEATURES_CX (1 << 0 | 1 << 9 | 1 << 13  | 1 << 19 | 1 << 20 | 1 << 23)
                         // LAHF/SAHF
#define V2_EXT_FEATURES_CX (1 << 0)

	{APMULLW, ymm, Py1, opBytes{0xd5, Pe, 0xd5}},
	{APMULULQ, ymm, Py1, opBytes{0xf4, Pe, 0xf4}},
	{APOPAL, ynone, P32, opBytes{0x61}},
	{APOPAW, ynone, Pe, opBytes{0x61}},
	{APOPCNTW, yml_rl, Pef3, opBytes{0xb8}},
	{APOPCNTL, yml_rl, Pf3, opBytes{0xb8}},
	{APOPCNTQ, yml_rl, Pfw, opBytes{0xb8}},
	{APOPFL, ynone, P32, opBytes{0x9d}},
	{APOPFQ, ynone, Py, opBytes{0x9d}},
	{APOPFW, ynone, Pe, opBytes{0x9d}},

	}
	return false
}
func rewriteValueS390X_OpPopCount16(v *Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (PopCount16 x)
	// result: (MOVBZreg (SumBytes2 (POPCNT <typ.UInt16> x)))
	for {
		x := v_0
		v.reset(OpS390XMOVBZreg)
		v0 := b.NewValue0(v.Pos, OpS390XSumBytes2, typ.UInt8)
		v1 := b.NewValue0(v.Pos, OpS390XPOPCNT, typ.UInt16)
		v1.AddArg(x)
		v0.AddArg(v1)

// CHECK:       %[[POP_CNT:.*]] = "tf.PopulationCount"(%[[ARG_0]]) : (tensor<8xi32>) -> tensor<8xui8>
// CHECK:       %[[RES:.*]] = "tf.Cast"(%[[POP_CNT]]) <{Truncate = false}> : (tensor<8xui8>) -> tensor<8xi32>
// CHECK:       return %[[RES]]
// CHECK:         }
func.func @convert_population_count_i32(%arg0: tensor<8xi32>) -> tensor<8xi32> {
  %0 = "mhlo.popcnt"(%arg0) : (tensor<8xi32>) -> tensor<8xi32>

	// load on condition
	{i: 25, as: ALOCGR, a1: C_SCON, a2: C_REG, a6: C_REG},

	// find leftmost one
	{i: 8, as: AFLOGR, a1: C_REG, a6: C_REG},

	// population count
	{i: 9, as: APOPCNT, a1: C_REG, a6: C_REG},

	// compare
	{i: 70, as: ACMP, a1: C_REG, a6: C_REG},
	{i: 71, as: ACMP, a1: C_REG, a6: C_LCON},
	{i: 70, as: ACMPU, a1: C_REG, a6: C_REG},
	{i: 71, as: ACMPU, a1: C_REG, a6: C_LCON},