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Results 31 - 36 of 36 for input_size (0.24 sec)

  1. platforms/core-execution/persistent-cache/src/main/java/org/gradle/cache/internal/btree/BTreePersistentIndexedCache.java

            private IndexRoot root;
    
            @Override
            protected byte getType() {
                return 0x77;
            }
    
            @Override
            protected int getSize() {
                return Block.INT_SIZE + Block.LONG_SIZE + (3 * Block.LONG_SIZE) * maxChildIndexEntries;
            }
    
            @Override
            public void read(DataInputStream instr) throws IOException {
                int count = instr.readInt();
    Registered: Wed Jun 12 18:38:38 UTC 2024
    - Last Modified: Fri Sep 22 09:08:47 UTC 2023
    - 26.5K bytes
    - Viewed (0)
  2. src/internal/fuzz/fuzz.go

    						// at least one new coverage bit.
    						c.queueForMinimization(result, keepCoverage)
    					} else {
    						// Update the coordinator's coverage mask and save the value.
    						inputSize := len(result.entry.Data)
    						entryNew, err := c.addCorpusEntries(true, result.entry)
    						if err != nil {
    							stop(err)
    							break
    						}
    						if !entryNew {
    							if shouldPrintDebugInfo() {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 26 19:58:28 UTC 2024
    - 34.1K bytes
    - Viewed (0)
  3. src/crypto/sha512/sha512block_amd64.s

    // Aleksey Sidorov <******@****.***>
    
    #define YFER_SIZE (4*8)
    #define SRND_SIZE (1*8)
    #define INP_SIZE (1*8)
    
    #define frame_YFER (0)
    #define frame_SRND (frame_YFER + YFER_SIZE)
    #define frame_INP (frame_SRND + SRND_SIZE)
    #define frame_INPEND (frame_INP + INP_SIZE)
    
    #define addm(p1, p2) \
    	ADDQ p1, p2; \
    	MOVQ p2, p1
    
    #define COPY_YMM_AND_BSWAP(p1, p2, p3) \
    	VMOVDQU p2, p1;    \
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 27K bytes
    - Viewed (0)
  4. src/crypto/sha256/sha256block_amd64.s

    #define y0 R13
    #define y1 R14
    #define y2 R15
    #define y3 DI
    
    // Offsets
    #define XFER_SIZE 2*64*4
    #define INP_END_SIZE 8
    #define INP_SIZE 8
    
    #define _XFER 0
    #define _INP_END _XFER + XFER_SIZE
    #define _INP _INP_END + INP_END_SIZE
    #define STACK_SIZE _INP + INP_SIZE
    
    #define ROUND_AND_SCHED_N_0(disp, a, b, c, d, e, f, g, h, XDWORD0, XDWORD1, XDWORD2, XDWORD3) \
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 47.3K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/tf2xla/tests/legalize-tf.mlir

        // CHECK-SAME: batch_group_count = 1 : i64
        // CHECK-SAME: feature_group_count = 1 : i64
        // CHECK: return %[[RESULT]]
      %input_sizes = "tf.Const" () { value = dense<[100,28,28,1]> : tensor<4xi32> } : () -> tensor<4xi32>
      %result = "tf.Conv2DBackpropInput"(%input_sizes, %filter, %out_backprop) {
        data_format = "NHWC",
        dilations = [1, 1, 1, 1],
        explicit_paddings = [],
        padding = "VALID",
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon May 06 18:46:23 UTC 2024
    - 335.5K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/tensorflow/ir/tf_generated_ops.td

      }];
    
      let arguments = (ins
        Arg<TF_Int32Tensor, [{An integer vector representing the shape of `input`,
    where `input` is a 4-D `[batch, height, width, channels]` tensor.}]>:$input_sizes,
        Arg<TensorOf<[TF_Bfloat16, TF_Float16, TF_Float32, TF_Float64, TF_Int32]>, [{4-D with shape
    `[filter_height, filter_width, in_channels, out_channels]`.}]>:$filter,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 11 23:24:08 UTC 2024
    - 793K bytes
    - Viewed (0)
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