// Code generated by avx512test. DO NOT EDIT.

#include "../../../../../../runtime/textflag.h"

TEXT asmtest_avx512_vbmi(SB), NOSPLIT, $0
	VPERMB X26, X20, K1, X23                           // 62825d018dfa
	VPERMB X19, X20, K1, X23                           // 62a25d018dfb
	VPERMB X0, X20, K1, X23                            // 62e25d018df8
	VPERMB 7(SI)(DI*4), X20, K1, X23                   // 62e25d018dbcbe07000000

Lexp_dec_loop MOVUPS -16(BX), X0 MOVUPS X0, 16(DX) RET // func _expand_key_128<>() // Requires: SSE, SSE2 TEXT _expand_key_128<>(SB), NOSPLIT, $0 PSHUFD $0xff, X1, X1 SHUFPS $0x10, X0, X4 PXOR X4, X0 SHUFPS $0x8c, X0, X4 PXOR X4, X0 PXOR X1, X0 MOVUPS X0, (BX) ADDQ $0x10, BX RET // func _expand_key_192a<>() // Requires: SSE, SSE2 TEXT _expand_key_192a<>(SB), NOSPLIT, $0 PSHUFD $0x55, X1, X1 SHUFPS $0x10, X0, X4 PXOR X4, X0 SHUFPS $0x8c, X0, X4 PXOR X4, X0 PXOR X1, X0 MOVAPS X2, X5 MOVAPS X2, X6 PSLLDQ...

// In case of index mode instructions, usage of
// (Rx)(R0) is equivalent to (Rx+R0)
// In case of base+displacement mode instructions if
// the offset is 0, usage of (Rx) is equivalent to 0(Rx)
TEXT asmtest(SB),DUPOK|NOSPLIT,$0
	// move constants
	MOVD $1, R3                     // 38600001
	MOVD $-1, R4                    // 3880ffff
	MOVD $65535, R5                 // 6005ffff
	MOVD $65536, R6                 // 3cc00001

// and they are consistent with disassembler decoding.
// TODO means they cannot be handled by current assembler.

#include "../../../../../runtime/textflag.h"

TEXT asmtest(SB),DUPOK|NOSPLIT,$-8

	AND $(1<<63), R1                           // AND $-9223372036854775808, R1     // 21004192
	ADCW ZR, R8, R10                           // 0a011f1a
	ADC R0, R2, R12                            // 4c00009a

// the old assembler's (5a's) grammar and hand-writing complete
// instructions for each rule, to guarantee we cover the same space.

#include "../../../../../runtime/textflag.h"

TEXT	foo(SB), DUPOK|NOSPLIT, $0

// ADD
//
//	LTYPE1 cond imsr ',' spreg ',' reg
//	{
//		outcode($1, $2, &$3, $5, &$7);
//	}
// Cover some operand space here too.
	ADD	$1, R2, R3
	ADD	R1<<R2, R3, R4
	ADD	R1>>R2, R3, R4

// license that can be found in the LICENSE file.

// This input extends auto-generated amd64enc.s test suite
// with manually added tests.

#include "../../../../../runtime/textflag.h"

TEXT asmtest(SB),DUPOK|NOSPLIT,$0
	// AVX2GATHER: basic combinations.
	VPGATHERDQ Y2, (BP)(X7*2), Y1           // c4e2ed904c7d00
	VPGATHERDQ X12, (R13)(X14*2), X11       // c40299905c7500
	VPGATHERDQ Y12, (R13)(X14*2), Y11       // c4029d905c7500

// Copyright 2022 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

#include "../../../../../runtime/textflag.h"

TEXT asmtest(SB),DUPOK|NOSPLIT,$0
lable1:
	BFPT	1(PC)				// 00050048
	BFPT	lable1		// BFPT 2	// 1ffdff4b
	BFPT	FCC0, lable1	// BFPT FCC0, 2	// 1ff9ff4b
	BFPT	FCC7, lable1	// BFPT FCC7, 2	// fff5ff4b

lable2:
	BFPF	1(PC)				// 00040048

// the old assembler's (7a's) grammar and hand-writing complete
// instructions for each rule, to guarantee we cover the same space.

#include "../../../../../runtime/textflag.h"

TEXT	foo(SB), DUPOK|NOSPLIT, $-8

// arithmetic operations
	ADDW	$1, R2, R3
	ADDW	R1, R2, R3
	ADDW	R1, ZR, R3
	ADD	$1, R2, R3
	ADD	R1, R2, R3
	ADD	R1, ZR, R3
	ADD	$1, R2, R3
	ADDW	$1, R2
	ADDW	R1, R2
	ADD	$1, R2

// Code generated by avx512test. DO NOT EDIT.

#include "../../../../../../runtime/textflag.h"

TEXT asmtest_avx512_vbmi2(SB), NOSPLIT, $0
	VPCOMPRESSB X7, K1, X15                            // 62d27d0963ff
	VPCOMPRESSB X13, K1, X15                           // 62527d0963ef
	VPCOMPRESSB X8, K1, X15                            // 62527d0963c7
	VPCOMPRESSB X7, K1, X28                            // 62927d0963fc

// Copyright 2019 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

#include "../../../../../runtime/textflag.h"

TEXT asmtest(SB),DUPOK|NOSPLIT,$0
start:
	//
	// Unprivileged ISA
	//

	// 2.4: Integer Computational Instructions

	ADDI	$2047, X5				// 9382f27f
	ADDI	$-2048, X5				// 93820280
	ADDI	$2048, X5				// 9382024093820240