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Results 21 - 30 of 108 for vsubfp (0.25 sec)
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src/cmd/internal/obj/arm/a.out.go
ABVC ABHI ABLS ABGE ABLT ABGT ABLE AMOVWD AMOVWF AMOVDW AMOVFW AMOVFD AMOVDF AMOVF AMOVD ACMPF ACMPD AADDF AADDD ASUBF ASUBD AMULF AMULD ANMULF ANMULD AMULAF AMULAD ANMULAF ANMULAD AMULSF AMULSD ANMULSF ANMULSD AFMULAF AFMULAD AFNMULAF AFNMULAD AFMULSF
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 05 16:22:12 UTC 2021 - 7K bytes - Viewed (0) -
src/html/entity.go
"varsupsetneqq;": {'\u2ACC', '\uFE00'}, "vnsub;": {'\u2282', '\u20D2'}, "vnsup;": {'\u2283', '\u20D2'}, "vsubnE;": {'\u2ACB', '\uFE00'}, "vsubne;": {'\u228A', '\uFE00'}, "vsupnE;": {'\u2ACC', '\uFE00'}, "vsupne;": {'\u228B', '\uFE00'}, }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jul 31 22:10:54 UTC 2018 - 114.3K bytes - Viewed (0) -
tensorflow/compiler/jit/deadness_analysis.cc
continue; } if (op->kind() == pred_kind) { // "Inline" the operands of an inner And/Or into the parent And/Or. for (Predicate* subop : op->GetOperands()) { if (simplified_ops_set.insert(subop).second) { simplified_ops.push_back(subop); } } } else { simplified_ops.push_back(op); } } if (simplified_ops.size() == 1) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Mar 12 06:33:33 UTC 2024 - 60.4K bytes - Viewed (0) -
src/syscall/ztypes_linux_amd64.go
} const ( VINTR = 0x0 VQUIT = 0x1 VERASE = 0x2 VKILL = 0x3 VEOF = 0x4 VTIME = 0x5 VMIN = 0x6 VSWTC = 0x7 VSTART = 0x8 VSTOP = 0x9 VSUSP = 0xa VEOL = 0xb VREPRINT = 0xc VDISCARD = 0xd VWERASE = 0xe VLNEXT = 0xf VEOL2 = 0x10 IGNBRK = 0x1 BRKINT = 0x2 IGNPAR = 0x4 PARMRK = 0x8 INPCK = 0x10
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 08 17:55:49 UTC 2023 - 12K bytes - Viewed (0) -
src/syscall/ztypes_linux_386.go
} const ( VINTR = 0x0 VQUIT = 0x1 VERASE = 0x2 VKILL = 0x3 VEOF = 0x4 VTIME = 0x5 VMIN = 0x6 VSWTC = 0x7 VSTART = 0x8 VSTOP = 0x9 VSUSP = 0xa VEOL = 0xb VREPRINT = 0xc VDISCARD = 0xd VWERASE = 0xe VLNEXT = 0xf VEOL2 = 0x10 IGNBRK = 0x1 BRKINT = 0x2 IGNPAR = 0x4 PARMRK = 0x8 INPCK = 0x10
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 08 17:55:49 UTC 2023 - 11.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/transforms/push_transpose_through_ewise.cc
// broadcastable and fully static. Consider moving this into attribute later. bool IsElementwise(Operation *op) { if (!(llvm::isa<TFL::AddOp, TFL::MulOp, TFL::DivOp, TFL::SubOp, TFL::MaximumOp, TFL::MinimumOp>(op))) { return false; } auto opr1_type = llvm::dyn_cast_or_null<RankedTensorType>(op->getOperand(0).getType()); auto opr2_type =
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 12.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/quantization/tensorflow/fallback_to_flex_ops.cc
TF::Relu6Op::getOperationName().str(), TF::ReluOp::getOperationName().str(), TF::ReshapeOp::getOperationName().str(), TF::SoftmaxOp::getOperationName().str(), TF::SubOp::getOperationName().str(), TF::TransposeOp::getOperationName().str(), // go/keep-sorted end // clang-format on }); return *legacy_op_list; }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 12.2K bytes - Viewed (0) -
src/cmd/vendor/rsc.io/markdown/entity.go
"∝": "\u221d", "⊳": "\u22b3", "𝓋": "\U0001d4cb", "⫋︀": "\u2acb\ufe00", "⊊︀": "\u228a\ufe00", "⫌︀": "\u2acc\ufe00", "⊋︀": "\u228b\ufe00",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jan 24 13:01:26 UTC 2024 - 101K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
{name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true}, // arg0 + arg1 {name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true}, // arg0 + arg1 {name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF"}, // arg0 - arg1 {name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"}, // arg0 - arg1 {name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true}, // arg0 * arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:19 UTC 2023 - 25.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go
{name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true}, // arg0 + arg1 {name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true}, // arg0 + arg1 {name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF"}, // arg0 - arg1 {name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"}, // arg0 - arg1 {name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true}, // arg0 * arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 03:36:31 UTC 2023 - 25.5K bytes - Viewed (0)