}

  // Checks the expected result of shape inference for the given `op`.
  void CheckOutputShapes(
      TFE_Op* op,
      const std::vector<absl::optional<std::vector<int64_t>>>& input_shapes_vec,
      const std::vector<TF_Tensor*>& input_tensors,
      const absl::optional<std::vector<int64_t>>& expected_shape) {
    // Create input_shapes.
    TF_ShapeAndTypeList* input_shapes =

     */
    @Override
    public Settings settings() {
        return client.settings();
    }

    /**
     * Gets term vectors for a document asynchronously.
     *
     * @param request the term vectors request
     * @return a future for the term vectors response
     */
    @Override
    public ActionFuture<TermVectorsResponse> termVectors(final TermVectorsRequest request) {

        .createTestSuite();
  }

  // We are testing Vector / testing our tests on Vector.
  @SuppressWarnings("JdkObsolete")
  private Test testsForVector() {
    return ListTestSuiteBuilder.using(
            new TestStringListGenerator() {
              @Override
              protected List<String> create(String[] elements) {
                return new Vector<>(MinimalCollection.of(elements));
              }
            })

	VWMACCUSVX	V2, X10, V0, V3			// d76125f8

	// 31.11.15: Vector Integer Merge Instructions
	VMERGEVVM	V1, V2, V0, V3			// d781205c
	VMERGEVXM	X10, V2, V0, V3			// d741255c
	VMERGEVIM	$15, V2, V0, V3			// d7b1275c

	// 31.11.16: Vector Integer Move Instructions
	VMVVV		V2, V3				// d701015e
	VMVVX		X10, V3				// d741055e
	VMVVI		$15, V3				// d7b1075e

	// 31.12.1: Vector Single-Width Saturating Add and Subtract

        @CsvSource({ "1000, 500, 1, 512", // Minimal sectors per alloc
                "1000, 500, 8, 512", // Typical configuration
                "1000, 500, 64, 512", // Large allocation units
                "1000, 500, 8, 4096", // 4K sectors
                "1000, 500, 16, 4096", // Large sectors and allocation
                "1000, 0, 8, 512", // No free space

            if (mechs != null) {
                final ASN1EncodableVector vector = new ASN1EncodableVector();
                for (final ASN1ObjectIdentifier mech : mechs) {
                    vector.add(mech);
                }
                fields.add(new DERTaggedObject(true, 0, new DERSequence(vector)));
            }
            final int ctxFlags = getContextFlags();
            if (ctxFlags != 0) {

  std::vector<tensorflow::string> tensor_id_data;
};

struct TF_ImportGraphDefResults {
  std::vector<TF_Output> return_tensors;
  std::vector<TF_Operation*> return_nodes;
  std::vector<const char*> missing_unused_key_names;
  std::vector<int> missing_unused_key_indexes;

  // Backing memory for missing_unused_key_names values.
  std::vector<tensorflow::string> missing_unused_key_names_data;

        @CsvSource({ "1000, 500, 600, 1, 512", // Minimal sectors per alloc
                "1000, 500, 600, 8, 512", // Typical configuration
                "1000, 500, 600, 64, 512", // Large allocation units
                "1000, 500, 600, 8, 4096", // 4K sectors
                "1000, 500, 600, 16, 4096", // Large sectors and allocation
                "1000, 0, 0, 8, 512", // No free space

	MOVL (AX)(X0*1), AX             // ERROR "invalid instruction"
	MOVL (AX)(Y0*1), AX             // ERROR "invalid instruction"
	// VSIB/VM is invalid without vector index.
	// TODO(quasilyte): improve error message (#21860).
	// "invalid VSIB address (missing vector index)"
	VPGATHERQQ Y2, (BP), Y1         // ERROR "invalid instruction"
	// AVX2GATHER mask/index/dest #UD cases.

Using `gotestjsonbuildtext=1` restores the 1.23 behavior.
This setting will be removed in a future release, Go 1.28 at the earliest.

Go 1.24 changed [`crypto/rsa`](/pkg/crypto/rsa) to require RSA keys to be at
least 1024 bits. This behavior can be controlled with the `rsa1024min` setting.
Using `rsa1024min=0` restores the Go 1.23 behavior.