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Results 21 - 30 of 100 for fadd32 (0.48 sec)
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src/cmd/compile/internal/ssa/rewritedec64.go
// match: (Mul64 x y) // result: (Int64Make (Add32 <typ.UInt32> (Mul32 <typ.UInt32> (Int64Lo x) (Int64Hi y)) (Add32 <typ.UInt32> (Mul32 <typ.UInt32> (Int64Hi x) (Int64Lo y)) (Select0 <typ.UInt32> (Mul32uhilo (Int64Lo x) (Int64Lo y))))) (Select1 <typ.UInt32> (Mul32uhilo (Int64Lo x) (Int64Lo y)))) for { x := v_0 y := v_1 v.reset(OpInt64Make) v0 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Jan 19 22:42:34 UTC 2023 - 65.3K bytes - Viewed (0) -
src/runtime/pprof/proto_test.go
map1, map2 = fake, fake } return } func TestConvertCPUProfile(t *testing.T) { addr1, addr2, map1, map2 := testPCs(t) b := []uint64{ 3, 0, 500, // hz = 500 5, 0, 10, uint64(addr1 + 1), uint64(addr1 + 2), // 10 samples in addr1 5, 0, 40, uint64(addr2 + 1), uint64(addr2 + 2), // 40 samples in addr2 5, 0, 10, uint64(addr1 + 1), uint64(addr1 + 2), // 10 samples in addr1 }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jan 31 23:21:53 UTC 2024 - 17K bytes - Viewed (0) -
tensorflow/compiler/mlir/tfrt/tests/hoist_invariant_ops.mlir
// CHECK-NEXT: "tf.AddV2"({{.*}}, [[v]]) {device = "/CPU:0"} : (tensor<i32>, tensor<i32>) -> tensor<i32> // CHECK-NEXT: return %const = "tf.Const"() {device = "/CPU:0", value = dense<0> : tensor<i32>} : () -> tensor<i32> %x = "tf.AddV2"(%const, %const) {device = "/CPU:0"} : (tensor<i32>, tensor<i32>) -> tensor<i32> %r = "tf.AddV2"(%arg, %x) {device = "/CPU:0"} : (tensor<i32>, tensor<i32>) -> tensor<i32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Apr 01 23:54:14 UTC 2024 - 18.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/promote_resources_to_args_functions.mlir
func.func @add_and_pack(%arg0: tensor<i1>) -> tensor<2xf32> { // CHECK-NOT: "tf.VarHandleOp" // CHECK-NOT: "tf.ReadVariableOp" // CHECK: %[[CONST:.*]] = "tf.Const"() // CHECK: %[[ADD:[0-9]*]] = "tf.AddV2"(%arg1, %[[CONST]]) // CHECK: %[[PACK:[0-9]*]] = "tf.Pack"(%[[CONST]], %[[ADD]]) // CHECK: return %[[PACK]] %0 = "tf.Const"() {value = dense<4.200000e+01> : tensor<f32>} : () -> tensor<f32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Mar 24 05:47:26 UTC 2022 - 1.7K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/mlir2graphdef/case.mlir
%0 = tf_executor.graph { %outputs, %control = tf_executor.island wraps "tf.Const"() {device = "", value = dense<1> : tensor<i32>} : () -> tensor<i32> %outputs_0, %control_1 = tf_executor.island wraps "tf.AddV2"(%arg0, %outputs) {device = ""} : (tensor<i32>, tensor<i32>) -> tensor<*xi32> tf_executor.fetch %outputs_0 : tensor<*xi32> } func.return %0 : tensor<*xi32> }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Mar 28 12:06:33 UTC 2022 - 2.5K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
"DIVWUCC", "DIVWUVCC", "DIVWUV", "MODUD", "MODUW", "MODSD", "MODSW", "EQV", "EQVCC", "EXTSB", "EXTSBCC", "EXTSH", "EXTSHCC", "FABS", "FABSCC", "FADD", "FADDCC", "FADDS", "FADDSCC", "FCMPO", "FCMPU", "FCTIW", "FCTIWCC", "FCTIWZ", "FCTIWZCC", "FDIV", "FDIVCC", "FDIVS", "FDIVSCC", "FMADD", "FMADDCC", "FMADDS", "FMADDSCC",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/lower-static-tensor-list.mlir
// CHECK-LABEL: func @otherVariantWhileBody // CHECK: [[CST:%.*]] = "tf.Const"() // CHECK-NEXT: [[ADD:%.*]] = "tf.AddV2"(%arg2, [[CST]]) // CHECK-NEXT: [[TENSOR_MAP_INSERT_RESULT:%.*]] = "tf.TensorMapInsert"(%arg3, %arg2, %arg2) // CHECK-NEXT: [[ADD_2:%.*]] = "tf.AddV2"(%arg0, [[CST]]) // CHECK-NEXT: return [[ADD_2]], %arg1, [[ADD]], [[TENSOR_MAP_INSERT_RESULT]]
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 39.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/resource_op_lifting.mlir
// CHECK-NEXT: %[[ADD2:.*]] = "tf.AddV2"(%[[BARG0]], %[[DELTA]]) %add2 = "tf.AddV2"(%arg0, %constant) : (tensor<i32>, tensor<i32>) -> tensor<i32> // CHECK-NEXT: return %[[ADD2]], %[[ADD1]] %id = "tf.Identity"(%arg2) : (tensor<*x!tf_type.resource<tensor<f32>>>) -> tensor<*x!tf_type.resource<tensor<f32>>>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 74K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/tests/cast_bf16_ops_to_f32.mlir
// CHECK: return %[[identity]] : tensor<1x1x2xf32> // Tests that an AddV2 op accepting two bf16 operands is transformed into // an AddV2 op that accepts two fp32 operands. func.func @cast_bf16_add_v2_to_fp32(%arg0: tensor<2xbf16>, %arg1: tensor<2xbf16>) -> tensor<2xf32> { %0 = "tf.AddV2"(%arg0, %arg1) : (tensor<2xbf16>, tensor<2xbf16>) -> tensor<2xbf16>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 8.4K bytes - Viewed (0) -
src/math/rand/v2/rand.go
hi, lo1b := bits.Mul32(uint32(x>>32), n) lo1, c := bits.Add32(lo1a, lo1b, 0) hi += c if lo1 == 0 && lo0 < uint32(n) { n64 := uint64(n) thresh := uint32(-n64 % n64) for lo1 == 0 && lo0 < thresh { x := r.Uint64() lo1a, lo0 = bits.Mul32(uint32(x), n) hi, lo1b = bits.Mul32(uint32(x>>32), n) lo1, c = bits.Add32(lo1a, lo1b, 0) hi += c } } return hi }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:25:49 UTC 2024 - 12.8K bytes - Viewed (0)