CFLDSP	32(X5), F10				// ERROR "rs2 must be SP/X2"
	CFLDSP	32(SP), X10				// ERROR "expected float register in rd position"
	CFLDSP	36(SP), F10				// ERROR "must be a multiple of 8"
	CSWSP	X10, 20(X5)				// ERROR "rd must be SP/X2"
	CSWSP	F10, 20(SP)				// ERROR "expected integer register in rs2 position"
	CSWSP	X10, 22(SP)				// ERROR "must be a multiple of 4"
	CSDSP	X10, 24(X5)				// ERROR "rd must be SP/X2"

	{"g", "R14"},
	{"SI", "SI"},
	{"SP", "SP"},
	{"X0", "X0"},
	{"X1", "X1"},
	{"X10", "X10"},
	{"X11", "X11"},
	{"X12", "X12"},
	{"X13", "X13"},
	{"X14", "X14"},
	{"X15", "X15"},
	{"X2", "X2"},
	{"X3", "X3"},
	{"X4", "X4"},
	{"X5", "X5"},
	{"X6", "X6"},
	{"X7", "X7"},
	{"X8", "X8"},
	{"X9", "X9"},
	{"_expand_key_128<>(SB)", "_expand_key_128<>(SB)"},
	{"_seek<>(SB)", "_seek<>(SB)"},

PSHUFB X0, X1 ADDQ $0x01, SI ADCQ $0x00, DI MOVQ SI, X2 PINSRQ $0x01, DI, X2 PSHUFB X0, X2 MOVUPS (CX), X0 PXOR X0, X1 PXOR X0, X2 ADDQ $0x10, CX SUBQ $0x0c, AX JE enc192 JB enc128 MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 ADDQ $0x20, CX enc192: MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 ADDQ $0x20, CX enc128: MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 MOVUPS...

// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

TEXT errors(SB),$0
	VSHUF4IV	$16, V1, V2	// ERROR "operand out of range 0 to 15"
	XVSHUF4IV	$16, X1, X2	// ERROR "operand out of range 0 to 15"
	ADDV16		$1, R4, R5	// ERROR "the constant must be a multiple of 65536."
	ADDV16		$65535, R4, R5	// ERROR "the constant must be a multiple of 65536."

PSHUFB X0, X1 ADDQ $0x01, SI ADCQ $0x00, DI MOVQ SI, X2 PINSRQ $0x01, DI, X2 PSHUFB X0, X2 MOVUPS (CX), X0 PXOR X0, X1 PXOR X0, X2 ADDQ $0x10, CX SUBQ $0x0c, AX JE enc192 JB enc128 MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 ADDQ $0x20, CX enc192: MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 ADDQ $0x20, CX enc128: MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 MOVUPS...

        //
        // To determine which side of logFloor.5 the logarithm is,
        // we compare x^2 to 2^(2 * logFloor + 1).
        BigInteger x2 = x.pow(2);
        int logX2Floor = x2.bitLength() - 1;
        return (logX2Floor < 2 * logFloor + 1) ? logFloor : logFloor + 1;
    }
    throw new AssertionError();
  }

  /*

// in the usual way by the opcode itself. Asm must use AMRC for both instructions, so
// we return the opcode for MRC so that asm doesn't need to import obj/arm.
func ARMMRCOffset(op obj.As, cond string, x0, x1, x2, x3, x4, x5 int64) (offset int64, op0 obj.As, ok bool) {
	op1 := int64(0)
	if op == arm.AMRC {
		op1 = 1
	}
	bits, ok := ParseARMCondition(cond)
	if !ok {
		return
	}
	offset = (0xe << 24) | // opcode

   *     null}.
   */
  @Deprecated
  @J2ktIncompatible
  @GwtIncompatible // propagateIfInstanceOf
  public static <X1 extends Throwable, X2 extends Throwable> void propagateIfPossible(
      @Nullable Throwable throwable, Class<X1> declaredType1, Class<X2> declaredType2)
      throws X1, X2 {
    checkNotNull(declaredType2);
    propagateIfInstanceOf(throwable, declaredType1);
    propagateIfPossible(throwable, declaredType2);
  }

     * 1.0.0.RC1 < 1.0.0-RC2 and more generally:
     * 1.0.0.X1 < 1.0.0-X2 for any string X
     */
    @Test
    void testMng7644() {
        for (String x : new String[] {"abc", "alpha", "a", "beta", "b", "def", "milestone", "m", "RC"}) {
            // 1.0.0.X1 < 1.0.0-X2 for any string x
            checkVersionsOrder("1.0.0." + x + "1", "1.0.0-" + x + "2");

      retVal &= Enums.getIfPresent(enumType, sampleData[i & 255]).isPresent();
    }
    return retVal;
  }

  private enum SmallEnum {
    X0,
    X1,
    X2
  }

  private enum MediumEnum {
    X0,
    X1,
    X2,
    X3,
    X4,
    X5,
    X6,
    X7,
    X8,
    X9,
    X10,
    X11,
    X12,
    X13,
    X14,
    X15,
    X16,
    X17,