R6-R12. ADD $112, R5 // Load xk[28:35] and cipher LXVD2X (R0+R5), V1 LXVD2X (R6+R5), V2 VCIPHER V0, V1, V0 VCIPHER V0, V2, V0 // Load xk[36:43] and cipher LXVD2X (R7+R5), V1 LXVD2X (R8+R5), V2 BEQ CR1, Ldec_tail // Key size 10? VCIPHER V0, V1, V0 VCIPHER V0, V2, V0 // Load xk[44:51] and cipher LXVD2X (R9+R5), V1 LXVD2X (R10+R5), V2 BEQ CR2, Ldec_tail // Key size 12? VCIPHER V0, V1, V0 VCIPHER V0, V2, V0 // Load xk[52:59] and cipher LXVD2X (R11+R5), V1 LXVD2X (R12+R5), V2 BNE CR3, Linvalid_key_len // Not...

		a.Scale = int16(scale)
	}
}

// registerList parses an ARM or ARM64 register list expression, a list of
// registers in []. There may be comma-separated ranges or individual
// registers, as in [R1,R3-R5] or [V1.S4, V2.S4, V3.S4, V4.S4].
// For ARM, only R0 through R15 may appear.
// For ARM64, V0 through V31 with arrangement may appear.
//
// For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.