FNMADD:         "fnmadd",
	FNMADDCC:       "fnmadd.",
	FNMSUB:         "fnmsub",
	FNMSUBCC:       "fnmsub.",
	FRSP:           "frsp",
	FRSPCC:         "frsp.",
	FSUB:           "fsub",
	FSUBCC:         "fsub.",
	ISYNC:          "isync",
	LBZ:            "lbz",
	LBZU:           "lbzu",
	LBZUX:          "lbzux",
	LBZX:           "lbzx",
	LFD:            "lfd",
	LFDU:           "lfdu",

(Add32F x y) => (Select0 (FADDS x y))
(Add64F x y) => (Select0 (FADD x y))

(Sub(64|Ptr) ...) => (SUB ...)
(Sub(32|16|8) ...) => (SUBW ...)
(Sub32F x y) => (Select0 (FSUBS x y))
(Sub64F x y) => (Select0 (FSUB x y))

(Mul64 ...) => (MULLD ...)
(Mul(32|16|8) ...) => (MULLW ...)
(Mul32F ...) => (FMULS ...)
(Mul64F ...) => (FMUL ...)
(Mul64uhilo ...) => (MLGR ...)

(Div32F ...) => (FDIVS ...)
(Div64F ...) => (FDIV ...)

{"Name":"FSUB (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FSUB (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FSUB <Sd>, <Sn>, <Sm>","Code":"","Alias":""},

//
(Add(Ptr|64|32|16|8) ...) => (ADD ...)
(Add64F ...) => (FADD ...)
(Add32F ...) => (FADDS ...)

(Sub(Ptr|64|32|16|8) ...) => (SUB ...)
(Sub32F ...) => (FSUBS ...)
(Sub64F ...) => (FSUB ...)

(Min(32|64)F x y) && buildcfg.GOPPC64 >= 9 => (XSMINJDP x y)
(Max(32|64)F x y) && buildcfg.GOPPC64 >= 9 => (XSMAXJDP x y)

// Combine 64 bit integer multiply and adds

	//TODO: FSTPL (R11)                     // 41dd1b
	//TODO: FSTPT (BX)                      // db3b
	//TODO: FSTPT (R11)                     // 41db3b
	//TODO: FSUB F2, F0                     // d8e2
	//TODO: FSUB F3, F0                     // d8e3
	//TODO: FSUBR F0, F2                    // dcea
	//TODO: FSUBR F0, F3                    // dceb
	//TODO: FSUBS (BX)                      // d823

// license that can be found in the LICENSE file.

(Add(Ptr|64|32|16|8) ...) => (ADD ...)
(Add(32|64)F ...) => (FADD(S|D) ...)

(Sub(Ptr|64|32|16|8) ...) => (SUB ...)
(Sub(32|64)F ...) => (FSUB(S|D) ...)

(Mul64 ...) => (MUL ...)
(Mul(32|16|8) ...) => (MULW ...)
(Mul(32|64)F  ...) => (FMUL(S|D) ...)

(Hmul64  ...) => (MULH ...)
(Hmul64u ...) => (UMULH ...)

			break
		}
		x := v_0.Args[0]
		if x.Op != OpS390XFADD || !(b == x.Block) {
			break
		}
		v.reset(OpSelect1)
		v.AddArg(x)
		return true
	}
	// match: (LTDBR (Select0 x:(FSUB _ _)))
	// cond: b == x.Block
	// result: (Select1 x)
	for {
		if v_0.Op != OpSelect0 {
			break
		}
		x := v_0.Args[0]
		if x.Op != OpS390XFSUB || !(b == x.Block) {
			break
		}

		v.AuxInt = float64ToAuxInt(math.Sqrt(x))
		return true
	}
	return false
}
func rewriteValuePPC64_OpPPC64FSUB(v *Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (FSUB (FMUL x y) z)
	// cond: x.Block.Func.useFMA(v)
	// result: (FMSUB x y z)
	for {
		if v_0.Op != OpPPC64FMUL {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]

			outputs: []outputInfo{
				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "FSUB",
		argLen: 2,
		asm:    ppc64.AFSUB,
		reg: regInfo{
			inputs: []inputInfo{