the opcode. The possible settings of the condition code depend on the instruction.
CR0 is the default for fixed-point instructions; CR1 for floating point; CR6 for
vector instructions.

Example:

	ANDCC R3, R4, R5		<=>	and. r5, r3, r4 (set CR0)

4. Loads and stores from memory

In Go asm, opcodes starting with 'MOV' indicate a load or store. When the target

// Only CMPconst for these in case AND|OR|XOR result is > 32 bits
(SETBC [2] (CMPconst [0] a:(AND y z))) && a.Uses == 1 => (SETBC [2] (Select1 <types.TypeFlags> (ANDCC y z )))
(SETBCR [2] (CMPconst [0] a:(AND y z))) && a.Uses == 1 => (SETBCR [2] (Select1 <types.TypeFlags> (ANDCC y z )))

(SETBC [2] (CMPconst [0] o:(OR y z))) && o.Uses == 1 => (SETBC [2] (Select1 <types.TypeFlags> (ORCC y z )))

	ADDZE	R19
	ADDC	R9, R18
	ADDZE	R19, R9
	MOVD	R10, 0(R3)	// z[i]
	MOVD	R14, 8(R3)	// z[i+1]
	MOVD	R16, 16(R3)	// z[i+2]
	MOVD	R18, 24(R3)	// z[i+3]
	ADD	$32, R3
	ADD	$32, R4
	BDNZ	loop

	ANDCC	$3, R6
tail:
	CMP	R6, $0
	BEQ	done
	MOVD	R6, CTR
	PCALIGN $16
tailloop:
	MOVD	0(R4), R14
	MOVD	0(R3), R15
	MULLD	R5, R14, R10
	MULHDU	R5, R14, R11
	ADDC	R15, R10
	ADDZE	R11

			break
		}
		// Rewrite SUB $const,... into ADD $-const,...
		p.From.Offset = -p.From.Offset
		p.As = AADD
		// This is now an ADD opcode, try simplifying it below.
		fallthrough

	// Rewrite ADD/OR/XOR/ANDCC $const,... forms into ADDIS/ORIS/XORIS/ANDISCC
	case AADD:
		// Don't rewrite if this is not adding a constant value, or is not an int32

		v.AuxInt = int64ToAuxInt(1)
		v.AddArg(a)
		return true
	}
	// match: (SETBC [2] (CMPconst [0] a:(AND y z)))
	// cond: a.Uses == 1
	// result: (SETBC [2] (Select1 <types.TypeFlags> (ANDCC y z )))
	for {
		if auxIntToInt32(v.AuxInt) != 2 || v_0.Op != OpPPC64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 {
			break
		}
		a := v_0.Args[0]
		if a.Op != OpPPC64AND {
			break
		}

	ADDECC
	ADDEO
	ADDEOCC
	LI
	ADDI
	ADDIC
	ADDICCC
	LIS
	ADDIS
	ADDME
	ADDMECC
	ADDMEO
	ADDMEOCC
	ADDZE
	ADDZECC
	ADDZEO
	ADDZEOCC
	AND
	ANDCC
	ANDC
	ANDCCC
	ANDICC
	ANDISCC
	B
	BA
	BL
	BLA
	BC
	BCA
	BCL
	BCLA
	BCCTR
	BCCTRL
	BCLR
	BCLRL
	CMPW
	CMPD
	CMP
	CMPWI

	opCC.AddArgs(op.Args...)
	op.reset(OpSelect0)
	op.AddArgs(opCC)
	return op
}

// Try converting a RLDICL to ANDCC. If successful, return the mask otherwise 0.
func convertPPC64RldiclAndccconst(sauxint int64) int64 {
	r, _, _, mask := DecodePPC64RotateMask(sauxint)
	if r != 0 || mask&0xFFFF != mask {
		return 0
	}

			},
			outputs: []outputInfo{
				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "ANDCC",
		argLen:      2,
		commutative: true,
		asm:         ppc64.AANDCC,
		reg: regInfo{
			inputs: []inputInfo{