[6]*argField{ap_VecReg_6_10, ap_Reg_16_20}},
	{MTVSRBMI, 0xfc00003e00000000, 0x1000001400000000, 0x0, // Move To VSR Byte Mask Immediate DX-form (mtvsrbmi VRT,bm)
		[6]*argField{ap_VecReg_6_10, ap_ImmUnsigned_16_25_11_15_31_31}},
	{MTVSRDM, 0xfc1f07ff00000000, 0x1013064200000000, 0x0, // Move to VSR Doubleword Mask VX-form (mtvsrdm VRT,RB)

	// We have 256 free cidrs
	a, err := NewCIDRSet(clusterCIDR, 24)
	if err != nil {
		t.Fatalf("unexpected error creating CidrSet: %v", err)
	}

	clusterMaskSize, _ := clusterCIDR.Mask.Size()
	max := getMaxCIDRs(24, clusterMaskSize)
	em := testMetrics{
		usage:      0,
		allocs:     0,
		releases:   0,
		allocTries: 0,
		max:        float64(max),
	}
	expectMetrics(t, cidr, em)

// license that can be found in the LICENSE file.

package template

import (
	"strings"
)

// attrTypeMap[n] describes the value of the given attribute.
// If an attribute affects (or can mask) the encoding or interpretation of
// other content, or affects the contents, idempotency, or credentials of a
// network message, then the value in this map is contentTypeUnsafe.
// This map is derived from HTML5, specifically

			}
			expected := (i + 7) / 8
			if reader.n != expected {
				t.Errorf("Int(reader, %d) should read %d bytes, but it read: %d", max, expected, reader.n)
			}
		})
	}
}

// Test that Int does not mask out valid return values
func TestIntMask(t *testing.T) {
	for max := 1; max <= 256; max++ {
		t.Run(fmt.Sprintf("max=%d", max), func(t *testing.T) {
			for i := 0; i < max; i++ {
				if testing.Short() && i == 0 {

// from stopped via the core dump bit.

const (
	mask    = 0x7F
	core    = 0x80
	exited  = 0x00
	stopped = 0x7F
	shift   = 8
)

func (w WaitStatus) Exited() bool { return w&mask == exited }

func (w WaitStatus) Signaled() bool { return w&mask != stopped && w&mask != exited }

func (w WaitStatus) Stopped() bool { return w&0xFF == stopped }

	// of "bad words" being formed.
	alphanums = "bcdfghjklmnpqrstvwxz2456789"
	// No. of bits required to index into alphanums string.
	alphanumsIdxBits = 5
	// Mask used to extract last alphanumsIdxBits of an int.
	alphanumsIdxMask = 1<<alphanumsIdxBits - 1
	// No. of random letters we can extract from a single int63.
	maxAlphanumsPerInt = 63 / alphanumsIdxBits
)

        return false;
      }

      int longIndex = (int) (bitIndex >>> LONG_ADDRESSABLE_BITS);
      long mask = 1L << bitIndex; // only cares about low 6 bits of bitIndex

      long oldValue;
      long newValue;
      do {
        oldValue = data.get(longIndex);
        newValue = oldValue | mask;
        if (oldValue == newValue) {
          return false;
        }

// spec in the given pod spec with type set in mask. If visitor returns false,
// visiting is short-circuited. VisitContainers returns true if visiting completes,
// false if visiting was short-circuited.
func VisitContainers(podSpec *api.PodSpec, mask ContainerType, visitor ContainerVisitor) bool {
	if mask&InitContainers != 0 {
		for i := range podSpec.InitContainers {

			}
			if v.commutative {
				fmt.Fprintln(w, "commutative: true,")
			}
			if v.resultInArg0 {
				fmt.Fprintln(w, "resultInArg0: true,")
				// OpConvert's register mask is selected dynamically,
				// so don't try to check it in the static table.
				if v.name != "Convert" && v.reg.inputs[0] != v.reg.outputs[0] {

Some non-simple shifts have operands in the Go assembly which don't map directly
onto operands in the PPC64 assembly. When an operand in a shift instruction in the
Go assembly is a bit mask, that mask is represented as a start and end bit in the
PPC64 assembly instead of a mask. See the ISA for more detail on these types of shifts.
Here are a few examples:

	RLWMI $7,R3,$65535,R6 	=>	rlwimi r6,r3,7,16,31
	RLDMI $0,R4,$7,R6 		=>	rldimi r6,r4,0,61