ivhi+40(FP), IV_HIGH_LE {{/* Prepare plain from IV and blockIndex. */}} {{/* Copy to plaintext registers. */}} {{ range $i := xrange $N }} REV IV_LOW_LE, IV_LOW_BE REV IV_HIGH_LE, IV_HIGH_BE {{- /* https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/MOV--vector--from-general- */}} VMOV IV_LOW_BE, V{{ block_reg $i }}.D[1] VMOV IV_HIGH_BE, V{{ block_reg $i }}.D[0] {{- if ne (add $i 1) $N }} ADDS $1, IV_LOW_LE ADC $0, IV_HIGH_LE {{ end }} {{ end }} {{/* Num rounds branching. */}}...

ivhi+40(FP), IV_HIGH_LE {{/* Prepare plain from IV and blockIndex. */}} {{/* Copy to plaintext registers. */}} {{ range $i := xrange $N }} REV IV_LOW_LE, IV_LOW_BE REV IV_HIGH_LE, IV_HIGH_BE {{- /* https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/MOV--vector--from-general- */}} VMOV IV_LOW_BE, V{{ block_reg $i }}.D[1] VMOV IV_HIGH_BE, V{{ block_reg $i }}.D[0] {{- if ne (add $i 1) $N }} ADDS $1, IV_LOW_LE ADC $0, IV_HIGH_LE {{ end }} {{ end }} {{/* Num rounds branching. */}}...

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github.com/minio/md5-simd
https://github.com/minio/md5-simd
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                                 Apache License
                           Version 2.0, January 2004