tf_device.return %12 : tensor<f32>
  }
  return %1#0, %1#1, %1#2, %1#3 : tensor<f32>, tensor<f32>, tensor<f32>, tensor<f32>
}
func.func private @_func(%arg0: tensor<f32>, %arg1: tensor<f32>, %arg2: tensor<f32>) -> tensor<f32> {
  %0 = "tf.Mul"(%arg0, %arg1) {device = "/device:TPU_REPLICATED_CORE:0"} : (tensor<f32>, tensor<f32>) -> tensor<f32>

  explicit TaggedValue(Func f32) : type_(FUNC), data_(f32) {}
  /// TaggedValue constructor for type FLOAT32.
  explicit TaggedValue(float f32) : type_(FLOAT32), data_(Float32(f32)) {}
  /// TaggedValue constructor for type INT64.
  explicit TaggedValue(int64_t i64) : type_(INT64), data_(Int64(i64)) {}
  /// TaggedValue constructor for type FLOAT32.
  explicit TaggedValue(Float32 f32) : type_(FLOAT32), data_(f32) {}

  %1 = "tfl.mul"(%0, %arg2) {fused_activation_function = "RELU6", per_device_costs = {CPU = 5.0 : f32, GPU = 1.0 : f32}, tac.device = "GPU"} : (tensor<1xf32>, tensor<1xf32>) -> tensor<1xf32>

    %outputs_4, %control_4 = tf_executor.island wraps "tf.OpA"() {_replication_info = "cluster", _xla_compile_device_type = "TPU", device = "", value = dense<3.0> : tensor<f32>} : () -> tensor<f32>
    %outputs_5, %control_5 = tf_executor.island(%control_4) wraps "tf.TPUReplicatedOutput"(%outputs_3) {device = "", index = -1 : i64, is_mirrored_variable = true, is_packed = false} : (tensor<f32>) -> (tensor<f32>)

  %cpu = corert.get_op_handler %ch "cpu"
  %0 = corert.executeop(%cpu) "tf.Relu"(%arg0) { T = f32 } : 1
  %arg1 = tfrt_fallback_async.corert_tensorhandle_to_fallback_tensor %arg1_th {_tfrt_cost = 1 : i64, device = "/CPU:0"} : (!corert.tensorhandle) -> (!tfrt_fallback.tf_tensor)
  %1 = tfrt_fallback_async.executeop key(0) cost(100) device("/CPU:0") "tf.Relu"(%arg1) { T = f32 } : 1
  tfrt.return

    // conversion, then dequantized during inference.
    // Activation: f32, Weight: qi8, Bias: f32
    WEIGHT_ONLY = 1;

    // Apply default dynamic range quantization. Quantized tensor value's
    // ranges are determined during graph runtime.
    // Activation: f32, Weight: qi8, Bias: f32
    POST_TRAINING_QUANTIZATION_DYNAMIC_RANGE = 2;

def FuseTransposeFCLhsToBatchMatmul : Pat<
  (TFL_BatchMatMulOp
    (TFL_FullyConnectedOp:$fc_output
      (TFL_TransposeOp TensorOf<[F32]>:$fc_lhs,
                       (Arith_ConstantOp:$perm_value $p0)),
      TensorOf<[F32]>:$fc_rhs,
      $bias, $TFL_AF_None, $TFL_FCWO_Default,
      $keep_num_dims, $asymmetric_quantize_inputs_fc
    ),
    $bmm_rhs, ConstBoolAttrTrue, $transpose_rhs,

^bb0(%arg0: tensor<1x2xf32>):
  %cst_0 = arith.constant dense<[1, 0]> : tensor<2xi32>
  %0 = "tfl.quantize"(%arg0){qtype = tensor<1x2x!quant.uniform<u8:f32, 1.0>>}: (tensor<1x2xf32>) -> (tensor<1x2x!quant.uniform<u8:f32, 1.0>>)
  %1 = "tfl.dequantize"(%0): (tensor<1x2x!quant.uniform<u8:f32, 1.0>>) -> (tensor<1x2xf32>)
  %2 = "tf.Transpose"(%1, %cst_0): (tensor<1x2xf32>, tensor<2xi32>) -> tensor<2x1xf32>
  func.return %2 : tensor<2x1xf32>

  // CHECK: %[[VAL_0:.*]] = "tf._FusedConv2D"(%arg2, %arg1, %arg0) <{data_format = "NHWC", dilations = [1, 1, 1, 1], epsilon = 0.000000e+00 : f32, explicit_paddings = [], fused_ops = ["BiasAdd"], num_args = 1 : i64, operandSegmentSizes = array<i32: 1, 1, 1, 0>, padding = "SAME", strides = [1, 1, 1, 1], use_cudnn_on_gpu = true}> {TArgs = [f32]} : (tensor<8x32x32x3xf32>, tensor<1x1x3x128xf32>, tensor<128xf32>) -> tensor<*xf32>

      return %0 : tensor<f32>
    }
  }
}
```

will be transformed into:

```mlir
module  {
  func @foo(%arg0: tensor<f32>) -> tensor<f32> {
    %0 = tf_executor.graph {
      %outputs, %control = tf_executor.island {
        %1 = "tf.opA"(%arg0) : (tensor<f32>) -> tensor<f32>
        tf_executor.yield %1 : tensor<f32>
      }
      tf_executor.fetch %outputs : tensor<f32>