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Results 241 - 250 of 465 for f32 (0.04 sec)
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tensorflow/compiler/mlir/tensorflow/tests/tpu_sharding_identification.mlir
tf_device.return %12 : tensor<f32> } return %1#0, %1#1, %1#2, %1#3 : tensor<f32>, tensor<f32>, tensor<f32>, tensor<f32> } func.func private @_func(%arg0: tensor<f32>, %arg1: tensor<f32>, %arg2: tensor<f32>) -> tensor<f32> { %0 = "tf.Mul"(%arg0, %arg1) {device = "/device:TPU_REPLICATED_CORE:0"} : (tensor<f32>, tensor<f32>) -> tensor<f32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Feb 20 19:07:52 UTC 2024 - 47.5K bytes - Viewed (0) -
tensorflow/cc/experimental/libtf/value.h
explicit TaggedValue(Func f32) : type_(FUNC), data_(f32) {} /// TaggedValue constructor for type FLOAT32. explicit TaggedValue(float f32) : type_(FLOAT32), data_(Float32(f32)) {} /// TaggedValue constructor for type INT64. explicit TaggedValue(int64_t i64) : type_(INT64), data_(Int64(i64)) {} /// TaggedValue constructor for type FLOAT32. explicit TaggedValue(Float32 f32) : type_(FLOAT32), data_(f32) {}
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Sat Apr 13 05:23:45 UTC 2024 - 20.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/experimental/tac/execution_metadata_exporter_test.cc
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 11 06:11:34 UTC 2024 - 6K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/executor_tpuv1_island_coarsening/executor_tpuv1_island_coarsening.mlir
%outputs_4, %control_4 = tf_executor.island wraps "tf.OpA"() {_replication_info = "cluster", _xla_compile_device_type = "TPU", device = "", value = dense<3.0> : tensor<f32>} : () -> tensor<f32> %outputs_5, %control_5 = tf_executor.island(%control_4) wraps "tf.TPUReplicatedOutput"(%outputs_3) {device = "", index = -1 : i64, is_mirrored_variable = true, is_packed = false} : (tensor<f32>) -> (tensor<f32>)
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Aug 02 03:15:59 UTC 2022 - 36.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/tfrt/tests/ir/testdata/test.mlir
%cpu = corert.get_op_handler %ch "cpu" %0 = corert.executeop(%cpu) "tf.Relu"(%arg0) { T = f32 } : 1 %arg1 = tfrt_fallback_async.corert_tensorhandle_to_fallback_tensor %arg1_th {_tfrt_cost = 1 : i64, device = "/CPU:0"} : (!corert.tensorhandle) -> (!tfrt_fallback.tf_tensor) %1 = tfrt_fallback_async.executeop key(0) cost(100) device("/CPU:0") "tf.Relu"(%arg1) { T = f32 } : 1 tfrt.return
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Mar 25 11:03:04 UTC 2022 - 496 bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/stablehlo/quantization_options.proto
// conversion, then dequantized during inference. // Activation: f32, Weight: qi8, Bias: f32 WEIGHT_ONLY = 1; // Apply default dynamic range quantization. Quantized tensor value's // ranges are determined during graph runtime. // Activation: f32, Weight: qi8, Bias: f32 POST_TRAINING_QUANTIZATION_DYNAMIC_RANGE = 2;
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Jun 22 02:20:05 UTC 2023 - 3.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/transforms/optimize_batch_matmul.td
def FuseTransposeFCLhsToBatchMatmul : Pat< (TFL_BatchMatMulOp (TFL_FullyConnectedOp:$fc_output (TFL_TransposeOp TensorOf<[F32]>:$fc_lhs, (Arith_ConstantOp:$perm_value $p0)), TensorOf<[F32]>:$fc_rhs, $bias, $TFL_AF_None, $TFL_FCWO_Default, $keep_num_dims, $asymmetric_quantize_inputs_fc ), $bmm_rhs, ConstBoolAttrTrue, $transpose_rhs,
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 09 23:44:09 UTC 2023 - 2.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/prepare-tf.mlir
^bb0(%arg0: tensor<1x2xf32>): %cst_0 = arith.constant dense<[1, 0]> : tensor<2xi32> %0 = "tfl.quantize"(%arg0){qtype = tensor<1x2x!quant.uniform<u8:f32, 1.0>>}: (tensor<1x2xf32>) -> (tensor<1x2x!quant.uniform<u8:f32, 1.0>>) %1 = "tfl.dequantize"(%0): (tensor<1x2x!quant.uniform<u8:f32, 1.0>>) -> (tensor<1x2xf32>) %2 = "tf.Transpose"(%1, %cst_0): (tensor<1x2xf32>, tensor<2xi32>) -> tensor<2x1xf32> func.return %2 : tensor<2x1xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed May 29 07:26:59 UTC 2024 - 59.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/fused_kernel_matcher.mlir
// CHECK: %[[VAL_0:.*]] = "tf._FusedConv2D"(%arg2, %arg1, %arg0) <{data_format = "NHWC", dilations = [1, 1, 1, 1], epsilon = 0.000000e+00 : f32, explicit_paddings = [], fused_ops = ["BiasAdd"], num_args = 1 : i64, operandSegmentSizes = array<i32: 1, 1, 1, 0>, padding = "SAME", strides = [1, 1, 1, 1], use_cudnn_on_gpu = true}> {TArgs = [f32]} : (tensor<8x32x32x3xf32>, tensor<1x1x3x128xf32>, tensor<128xf32>) -> tensor<*xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 13.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/g3doc/_includes/tf_passes.md
return %0 : tensor<f32> } } } ``` will be transformed into: ```mlir module { func @foo(%arg0: tensor<f32>) -> tensor<f32> { %0 = tf_executor.graph { %outputs, %control = tf_executor.island { %1 = "tf.opA"(%arg0) : (tensor<f32>) -> tensor<f32> tf_executor.yield %1 : tensor<f32> } tf_executor.fetch %outputs : tensor<f32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Aug 02 02:26:39 UTC 2023 - 96.4K bytes - Viewed (0)