MOVD	p_len+16(FP), R11  // len(p)

update:
	CMP	$16, R11
	BLT	less_than_16
	LDP.P	16(R13), (R8, R10)
	CRC32X	R8, R9
	CRC32X	R10, R9
	SUB	$16, R11

	JMP	update

less_than_16:
	TBZ $3, R11, less_than_8

	MOVD.P	8(R13), R10
	CRC32X	R10, R9

less_than_8:
	TBZ	$2, R11, less_than_4

	MOVWU.P	4(R13), R10
	CRC32W	R10, R9

less_than_4:
	TBZ	$1, R11, less_than_2

	MOVW	R4, 12(R13)
	MOVW	R5, 16(R13)
	MOVW	R6, 20(R13)
	MOVW	R7, 24(R13)
	MOVW	R8, 28(R13)
	MOVW	g, 32(R13)
	MOVW	R11, 36(R13)

	// Skip floating point registers on goarmsoftfp != 0.
	MOVB    runtime·goarmsoftfp(SB), R11
	CMP	$0, R11
	BNE     skipfpsave
	MOVD	F8, (40+8*0)(R13)
	MOVD	F9, (40+8*1)(R13)
	MOVD	F10, (40+8*2)(R13)
	MOVD	F11, (40+8*3)(R13)
	MOVD	F12, (40+8*4)(R13)

	MOVW $2, R4	// arg 5 - vers
	MOVW R4, 4(R13)
	ADD $4, R13	// pass arg 5 on stack
	SWI $SYS___sigaction_sigtramp
	SUB $4, R13
	MOVW.CS $3, R8	// crash on syscall failure
	MOVW.CS R8, (R8)
	RET

TEXT runtime·sigfwd(SB),NOSPLIT,$0-16
	MOVW	sig+4(FP), R0
	MOVW	info+8(FP), R1
	MOVW	ctx+12(FP), R2
	MOVW	fn+0(FP), R11
	MOVW	R13, R4
	SUB	$24, R13
	BIC	$0x7, R13 // alignment for ELF ABI
	BL	(R11)

	MOVW	Rq, 4(R13)
	MOVW	Rr, 8(R13)
	MOVW	Rs, 12(R13)
	MOVW	RM, 16(R13)

	MOVW	Rn, Rr			/* numerator */
	MOVW	g_m(g), Rq
	MOVW	m_divmod(Rq), Rq	/* denominator */
	BL  	runtime·udiv(SB)
	MOVW	Rr, RTMP
	MOVW	4(R13), Rq
	MOVW	8(R13), Rr
	MOVW	12(R13), Rs
	MOVW	16(R13), RM
	RET

TEXT runtime·_div(SB),NOSPLIT,$16-0
	NO_LOCAL_POINTERS
	MOVW	Rq, 4(R13)
	MOVW	Rr, 8(R13)
	MOVW	Rs, 12(R13)

	BL runtime·entersyscall(SB)
	MOVW trap+0(FP), R0 // sigcall num
	MOVW a1+4(FP), R1 // a1
	MOVW a2+8(FP), R2 // a2
	MOVW a3+12(FP), R3 // a3
	MOVW R13, R4
	MOVW $a4+16(FP), R13 // a4 to a6 are passed on stack
	SWI $0 // syscall
	MOVW R4, R13
	MOVW $0, R2
	BCS error6
	MOVW R0, r1+28(FP) // r1
	MOVW R1, r2+32(FP) // r2
	MOVW R2, err+36(FP) // err
	BL runtime·exitsyscall(SB)
	RET
error6:
	MOVW $-1, R3

				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "CMPW",
		argLen: 2,
		asm:    x86.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{

	MOVW	(g_stack+stack_hi)(R3), R13

	// make room for args, retval and g
	SUB	$24, R13

	// save g
	MOVW	g, R3
	MOVW	R3, 20(R13)

	// g = m->gsignal
	MOVW	m_gsignal(R0), g

	// load args and call sighandler
	ADD	$4,R13,R5
	MOVM.IA	[R1-R3], (R5)
	BL	runtime·sighandler(SB)
	MOVW	16(R13), R0			// retval

	// restore g
	MOVW	20(R13), g

	// call noted(R0)

//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	SUB	R14, R13	// 01ae6822
	SUBU	R14, R13	// 01ae6823
	SUBV	R4, R3		// 0064182e
	SUBVU	R4, R3		// 0064182f
//	LSUBW imm ',' rreg
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	SUB	$6512, R13	// 21ade690
	SUB	$-6512, R13	// 21ad1970
	SUBU	$6512, R13	// 25ade690
	SUBV	$9531, R16	// 6210dac5
	SUBV	$-9531, R13	// 61ad253b
	SUBVU	$9531, R16	// 6610dac5

	CMP	$0, R0
	BEQ	3(PC)
	MOVW	R0, ret+20(FP)
	RET

	// Paranoia: check that SP is as we expect. Use R13 to avoid linker 'fixup'
	NOP	R13	// tell vet SP/R13 changed - stop checking offsets
	MOVW	12(R13), R0
	MOVW	$1234, R1
	CMP	R0, R1
	BEQ	2(PC)
	BL	runtime·abort(SB)

	MOVW	0(R13), R8    // m
	MOVW	4(R13), R0    // g

	CMP	$0, R8
	BEQ	nog
	CMP	$0, R0
	BEQ	nog

	MOVW	R0, g

	LDP	-16(R4), (R6, R7)
	STP	(R12, R13), -16(R5)
	LDP	-32(R4), (R8, R9)
	LDP	-48(R4), (R10, R11)
	LDP.W	-64(R4), (R12, R13)
	SUB	R14, R5, R5
	SUBS	$128, R2, R2
	BLS	copy64_from_start

loop64_backward:
	STP	(R6, R7), -16(R5)
	LDP	-16(R4), (R6, R7)
	STP	(R8, R9), -32(R5)
	LDP	-32(R4), (R8, R9)
	STP	(R10, R11), -48(R5)
	LDP	-48(R4), (R10, R11)
	STP.W	(R12, R13), -64(R5)
	LDP.W	-64(R4), (R12, R13)