x := make([]int64, 1024)
	y := make([]int64, 1024)
	for i := 0; i < b.N; i++ {
		var s int64
		for i := range x {
			s ^= x[i] + y[i]
		}
		globl = s
	}
}

// Added for ppc64 extswsli on power9
func BenchmarkExtShift(b *testing.B) {
	x := make([]int32, 1024)
	for i := 0; i < b.N; i++ {
		var s int64
		for i := range x {
			s ^= int64(x[i]+32) * 8
		}
		globl = s
	}
}

// those as well. The minimum processor requirement is POWER8 (ISA 2.07).
// The struct is padded to avoid false sharing.
var PPC64 struct {
	_         CacheLinePad
	HasDARN   bool // Hardware random number generator (requires kernel enablement)
	HasSCV    bool // Syscall vectored (requires kernel enablement)
	IsPOWER8  bool // ISA v2.07 (POWER8)
	IsPOWER9  bool // ISA v3.00 (POWER9)
	IsPOWER10 bool // ISA v3.1  (POWER10)

	// ppc64x:-"AND","CLRLSLWI"
	h := (v32 & 0xFFFFF) << 2
	// ppc64x:"CLRLSLDI"
	i := (v64 & 0xFFFFFFFF) << 5
	// ppc64x:-"CLRLSLDI"
	i += (v64 & 0xFFFFFFF) << 38
	// ppc64x/power9:-"CLRLSLDI"
	i += (v64 & 0xFFFF00) << 10
	// ppc64x/power9:-"SLD","EXTSWSLI"
	j := int64(x32+32) * 8
	return f, g, h, i, j
}

func checkWidenAfterShift(v int64, u uint64) (int64, uint64) {

	// ppc64x:-".*MOVW"

// at compile-time

func constantConvert32(x float32) float32 {
	// amd64:"MOVSS\t[$]f32.3f800000\\(SB\\)"
	// s390x:"FMOVS\t[$]f32.3f800000\\(SB\\)"
	// ppc64x/power8:"FMOVS\t[$]f32.3f800000\\(SB\\)"
	// ppc64x/power9:"FMOVS\t[$]f32.3f800000\\(SB\\)"
	// ppc64x/power10:"XXSPLTIDP\t[$]1065353216, VS0"
	// arm64:"FMOVS\t[$]\\(1.0\\)"
	if x > math.Float32frombits(0x3f800000) {
		return -x
	}
	return x
}

	  (or mips64le.hardfloat and mips64le.softfloat) feature build tags.
	- For GOARCH=ppc64 or ppc64le,
	  GOPPC64=power8, power9, and power10 correspond to the
	  ppc64.power8, ppc64.power9, and ppc64.power10
	  (or ppc64le.power8, ppc64le.power9, and ppc64le.power10)
	  feature build tags.
	- For GOARCH=riscv64,
	  GORISCV64=rva20u64 and rva22u64 correspond to the riscv64.rva20u64

#endif
GLOBL indexbytevbperm<>+0(SB), RODATA, $16
#endif

// Some operations are endian specific, choose the correct opcode base on GOARCH.
// Note, _VCZBEBB is only available on power9 and newer.
#ifdef GOARCH_ppc64le
#define _LDBEX	MOVDBR
#define _LWBEX	MOVWBR
#define _LHBEX	MOVHBR
#define _VCZBEBB VCTZLSBB
#else
#define _LDBEX	MOVD
#define _LWBEX	MOVW
#define _LHBEX	MOVH

	_        CacheLinePad
	HasDARN  bool // Hardware random number generator (requires kernel enablement)
	HasSCV   bool // Syscall vectored (requires kernel enablement)
	IsPOWER8 bool // ISA v2.07 (POWER8)
	IsPOWER9 bool // ISA v3.00 (POWER9), implies IsPOWER8
	_        CacheLinePad
}

// S390X contains the supported CPU features of the current IBM Z
// (s390x) platform. If the current platform is not IBM Z then all

// Unrolled index2to16 loop by 4 on ppc64le/power9
// Work is still needed for a big endian
// implementation on power9.

//go:build ppc64 || ppc64le

#include "go_asm.h"
#include "textflag.h"

// Needed to swap LXVD2X loads to the correct
// byte order to work on POWER8.

#ifdef GOARCH_ppc64
DATA byteswap<>+0(SB)/8, $0x0001020304050607
DATA byteswap<>+8(SB)/8, $0x08090a0b0c0d0e0f
#else

opcodes which explicitly translate to one PPC64 machine instruction. Most common opcodes
are supported.

Some examples of how pseudo-op assembly changes with GOPPC64:

	Go asm                       GOPPC64 <= power9          GOPPC64 >= power10
	MOVD mypackage·foo(SB), R3   addis r2, r3, ...          pld r3, ...
	                             ld    r3, r3, ...

	MOVD 131072(R3), R4          addis r31, r4, 2           pld r4, 131072(r3)

		// Define GOPPC64_power8..N from cfg.PPC64.
		// We treat each powerpc version as a superset of functionality.
		switch cfg.GOPPC64 {
		case "power10":
			args = append(args, "-D", "GOPPC64_power10")
			fallthrough
		case "power9":
			args = append(args, "-D", "GOPPC64_power9")
			fallthrough
		default: // This should always be power8.
			args = append(args, "-D", "GOPPC64_power8")
		}
	}