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src/cmd/asm/internal/asm/testdata/ppc64.s
XOR $1234567, R5, R3 // 6ca300126863d687 XORIS $15, R3, R4 // 6c64000f XOR $983040, R3, R4 // 6c64000f // TODO: cleanup inconsistency of printing CMPx opcodes with explicit CR arguments. CMP R3, R4 // 7c232000 CMP R3, R0 // 7c230000 CMP R3, R0, CR1 // CMP R3,CR1,R0 // 7ca30000
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Oct 29 13:14:38 UTC 2024 - 51K bytes - Viewed (0) -
doc/asm.html
<code>softfloat</code>) is made available to assembly code by predefining either <code>GOMIPS64_hardfloat</code> or <code>GOMIPS64_softfloat</code>. </p> <h3 id="unsupported_opcodes">Unsupported opcodes</h3> <p> The assemblers are designed to support the compiler so not all hardware instructions are defined for all architectures: if the compiler doesn't generate it, it might not be there.
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Nov 28 19:15:27 UTC 2023 - 36.3K bytes - Viewed (0)