MOVW	R1, R6
	CMPBEQ	R6, $0, L29
	LTDBR	F2, F2
	BLTU	L50
	FMOVD	F2, F4
L14:
	MOVD	$·pow_x433<>+0(SB), R1
	FMOVD	0(R1), F7
	WFCHDBS	V4, V7, V3
	BEQ	L15
	WFADB	V7, V4, V3
	FSUB	F7, F3
	WFCEDBS	V4, V3, V3
	BEQ	L15
	LTDBR	F0, F0
	FMOVD	8(R9), F4
	BNE	L16
L13:
	LTDBR	F2, F2
	BLT	L18
L40:
	FMOVD	$0, F0
	WFMDB	V4, V0, V1
	BR	L1
L49:
	WFMDB	V0, V4, V1

	case FST, FSTP, FISTTP, FIST, FISTP, FBSTP:
		if len(args) == 1 {
			args = append(args, "st0")
		}

	case FLD, FXCH, FCOM, FCOMP, FIADD, FIMUL, FICOM, FICOMP, FISUBR, FIDIV, FUCOM, FUCOMP, FILD, FBLD, FADD, FMUL, FSUB, FSUBR, FISUB, FDIV, FDIVR, FIDIVR:
		if len(args) == 1 {
			args = []string{"st0", args[0]}
		}

	case MASKMOVDQU, MASKMOVQ, XLATB, OUTSB, OUTSW, OUTSD:
	FixSegment:
		for i := len(inst.Prefix) - 1; i >= 0; i-- {

	FMOVD	280(R5), F3
	WFMADB	V1, V2, V3, V2
	FMOVD	272(R5), F3
	WFMADB	V1, V4, V3, V4
L9:
	FMOVD	264(R5), F3
	FMUL	F4, F6
	FMOVD	256(R5), F4
	WFMADB	V1, V4, V3, V4
	FDIV	F6, F2
	LGDR	F4, R1
	FSUB	F3, F4
	FMOVD	248(R5), F6
	WFMSDB	V4, V6, V1, V4
	FMOVD	240(R5), F1
	FMOVD	232(R5), F6
	WFMADB	V4, V6, V1, V6
	FMOVD	224(R5), F1
	FMOVD	216(R5), F3
	WFMADB	V4, V3, V1, V3
	WFMDB	V4, V4, V1

	// FSUB <Sd>, <Sn>, <Sm>
	{0xffe0fc00, 0x1e203800, FSUB, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
	// FSUB <Dd>, <Dn>, <Dm>
	{0xffe0fc00, 0x1e603800, FSUB, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
	// FSUB <Vd>.<t>, <Vn>.<t>, <Vm>.<t>

	ADDW	R1, R2, R3            // b9f81032
	ADDW	$8192, R1             // a71a2000
	ADDW	$8192, R1, R2         // ec21200000d8
	ADDE	R1, R2                // b9880021
	SUB	R3, R4                // b9090043
	SUB	R3, R4, R5            // b9e93054
	SUB	$8192, R3             // a73be000
	SUB	$8192, R3, R4         // ec43e00000d9
	SUBC	R1, R2                // b90b0021
	SUBC	$1, R1, R2            // ec21ffff00db
	SUBC	R2, R3, R4            // b9eb2043

	FADDS F1, F2, F3                // ec62082a
	FADDSCC F1, F2, F3              // ec62082b
	FSUB F1, F2                     // fc420828
	FSUB F1, F2, F3                 // fc620828
	FSUBCC F1, F2, F3               // fc620829
	FSUBS F1, F2                    // ec420828
	FSUBS F1, F2, F3                // ec620828
	FSUBCC F1, F2, F3               // fc620829
	FSUBSCC F1, F2, F3              // ec620829

		fallthrough

	case FCMP, FCMPE:
		if _, ok := inst.Args[1].(Imm); ok {
			args[1] = "$(0.0)"
		}
		fallthrough

	case FADD, FSUB, FMUL, FNMUL, FDIV, FMAX, FMIN, FMAXNM, FMINNM, FCSEL, FMADD, FMSUB, FNMADD, FNMSUB:
		if strings.HasSuffix(op, "MADD") || strings.HasSuffix(op, "MSUB") {
			args[2], args[3] = args[3], args[2]
		}
		if r, ok := inst.Args[0].(Reg); ok {
			rno := uint16(r)

		{name: "SUB", argLength: 2, reg: gp21, asm: "SUB"},                                                 // arg0-arg1
		{name: "SUBCC", argLength: 2, reg: gp21, asm: "SUBCC", typ: "(Int,Flags)"},                         // arg0-arg1 sets CC
		{name: "SUBFCconst", argLength: 1, reg: gp11cxer, asm: "SUBC", aux: "Int64"},                       // auxInt - arg0 (carry is ignored)

		{name: "FSUBS", argLength: 2, reg: fp21clobber, typ: "(Float32,Flags)", asm: "FSUBS", resultInArg0: true},                    // fp32 arg0 - arg1
		{name: "FSUB", argLength: 2, reg: fp21clobber, typ: "(Float64,Flags)", asm: "FSUB", resultInArg0: true},                      // fp64 arg0 - arg1

	FSCALE:          "FSCALE",
	FSIN:            "FSIN",
	FSINCOS:         "FSINCOS",
	FSQRT:           "FSQRT",
	FST:             "FST",
	FSTP:            "FSTP",
	FSUB:            "FSUB",
	FSUBP:           "FSUBP",
	FSUBR:           "FSUBR",
	FSUBRP:          "FSUBRP",
	FTST:            "FTST",
	FUCOM:           "FUCOM",
	FUCOMI:          "FUCOMI",
	FUCOMIP:         "FUCOMIP",
	FUCOMP:          "FUCOMP",