(Mul64 ...) => (MUL ...)
(Mul(32|16|8) ...) => (MULW ...)
(Mul(32|64)F  ...) => (FMUL(S|D) ...)

(Hmul64  ...) => (MULH ...)
(Hmul64u ...) => (UMULH ...)
(Hmul32  x y) => (SRAconst (MULL <typ.Int64> x y) [32])
(Hmul32u x y) => (SRAconst (UMULL <typ.UInt64> x y) [32])
(Select0 (Mul64uhilo x y)) => (UMULH x y)
(Select1 (Mul64uhilo x y)) => (MUL x y)

(Div64 [false] x y) => (DIV  x y)
(Div32 [false] x y) => (DIVW x y)

{"Name":"UMULH","Bits":"1|0|0|1|1|0|1|1|1|1|0|Rm:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMULH <Xd>, <Xn>, <Xm>","Code":"","Alias":""},

			rel := obj.Addrel(c.cursym)

			rel.Off = int32(c.pc)
			rel.Siz = 4
			rel.Sym = p.To.Sym
			rel.Add = p.To.Offset
			rel.Type = objabi.R_ADDR
			o1 = 0
		}

	case 15: /* mul/mneg/umulh/umull r,[r,]r; madd/msub/fmadd/fmsub/fnmadd/fnmsub Rm,Ra,Rn,Rd */
		o1 = c.oprrr(p, p.As)

		rf := int(p.From.Reg)
		rt := int(p.To.Reg)
		var r int
		var ra int
		if p.From3Type() == obj.TYPE_REG {

	}
	return false
}
func rewriteValueARM64_OpSelect0(v *Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Select0 (Mul64uhilo x y))
	// result: (UMULH x y)
	for {
		if v_0.Op != OpMul64uhilo {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		v.reset(OpARM64UMULH)
		v.AddArg2(x, y)
		return true
	}

			},
			outputs: []outputInfo{
				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "UMULH",
		argLen:      2,
		commutative: true,
		asm:         arm64.AUMULH,
		reg: regInfo{
			inputs: []inputInfo{