- Sort Score
- Result 10 results
- Languages All
Results 11 - 19 of 19 for SQRTD (0.07 sec)
-
src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go
{name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64 {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD"}, // abs(arg0), float64 {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64 {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32 // shifts
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 03:36:31 UTC 2023 - 25.5K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go
{VNEG_EQ_F64, []int{1, 0}, "VNEG", "NEGD"}, {VABS_EQ_F32, []int{1, 0}, "VABS", "ABSF"}, {VABS_EQ_F64, []int{1, 0}, "VABS", "ABSD"}, {VSQRT_EQ_F32, []int{1, 0}, "VSQRT", "SQRTF"}, {VSQRT_EQ_F64, []int{1, 0}, "VSQRT", "SQRTD"}, {VCMP_EQ_F32, []int{1, 0}, "VCMP", "CMPF"}, {VCMP_EQ_F64, []int{1, 0}, "VCMP", "CMPD"}, {VCMP_E_EQ_F32, []int{1, 0}, "VCMP.E", "CMPF"}, {VCMP_E_EQ_F64, []int{1, 0}, "VCMP.E", "CMPD"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 11.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
{name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"}, // -arg0, float32 {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64 {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64 {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32 {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD"}, // abs(arg0), float64
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/armerror.s
NEGD F0, F1, F2 // ERROR "illegal combination" ABSF F0, F1, F2 // ERROR "illegal combination" ABSD F0, F1, F2 // ERROR "illegal combination" SQRTF F0, F1, F2 // ERROR "illegal combination" SQRTD F0, F1, F2 // ERROR "illegal combination" MOVF F0, F1, F2 // ERROR "illegal combination" MOVD F0, F1, F2 // ERROR "illegal combination" MOVDF F0, F1, F2 // ERROR "illegal combination"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Nov 03 14:06:21 UTC 2017 - 14.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64.rules
(RotateLeft64 x y) => (ROTRV x (NEGV <y.Type> y)) // unary ops (Neg(64|32|16|8) ...) => (NEGV ...) (Neg(32|64)F ...) => (NEG(F|D) ...) (Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x) (Sqrt ...) => (SQRTD ...) (Sqrt32 ...) => (SQRTF ...) // boolean ops -- booleans are represented with 0=false, 1=true (AndB ...) => (AND ...) (OrB ...) => (OR ...) (EqB x y) => (XOR (MOVVconst [1]) (XOR <typ.Bool> x y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 31.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS.rules
// unary ops (Neg(32|16|8) ...) => (NEG ...) (Neg(32|64)F ...) => (NEG(F|D) ...) (Com(32|16|8) x) => (NORconst [0] x) (Sqrt ...) => (SQRTD ...) (Sqrt32 ...) => (SQRTF ...) // TODO: optimize this case? (Ctz32NonZero ...) => (Ctz32 ...) // count trailing zero // 32 - CLZ(x&-x - 1)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 35.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64.rules
// unary ops (Neg(64|32|16|8) ...) => (NEGV ...) (Neg(32|64)F ...) => (NEG(F|D) ...) (Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x) (Sqrt ...) => (SQRTD ...) (Sqrt32 ...) => (SQRTF ...) // boolean ops -- booleans are represented with 0=false, 1=true (AndB ...) => (AND ...) (OrB ...) => (OR ...) (EqB x y) => (XOR (MOVVconst [1]) (XOR <typ.Bool> x y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 31 03:59:48 UTC 2023 - 41.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
(Or(32|16|8) ...) => (OR ...) (Xor(32|16|8) ...) => (XOR ...) // unary ops (Neg(32|16|8) x) => (RSBconst [0] x) (Neg(32|64)F ...) => (NEG(F|D) ...) (Com(32|16|8) ...) => (MVN ...) (Sqrt ...) => (SQRTD ...) (Sqrt32 ...) => (SQRTF ...) (Abs ...) => (ABSD ...) // TODO: optimize this for ARMv5 and ARMv6 (Ctz32NonZero ...) => (Ctz32 ...) (Ctz16NonZero ...) => (Ctz32 ...) (Ctz8NonZero ...) => (Ctz32 ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SQRTD", argLen: 1, asm: arm.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)