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Results 11 - 17 of 17 for ROLW (0.25 sec)

  1. src/cmd/compile/internal/ssa/_gen/AMD64.rules

    // rotate left negative = rotate right
    (ROLQ x (NEG(Q|L) y)) => (RORQ x y)
    (ROLL x (NEG(Q|L) y)) => (RORL x y)
    (ROLW x (NEG(Q|L) y)) => (RORW x y)
    (ROLB x (NEG(Q|L) y)) => (RORB x y)
    
    // rotate right negative = rotate left
    (RORQ x (NEG(Q|L) y)) => (ROLQ x y)
    (RORL x (NEG(Q|L) y)) => (ROLL x y)
    (RORW x (NEG(Q|L) y)) => (ROLW x y)
    (RORB x (NEG(Q|L) y)) => (ROLB x y)
    
    // rotate by constants
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 93.9K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/amd64enc.s

    	//TODO: RETFQ $0xf123                   // ca23f1
    	ROLW $1, (BX)                           // 66d103
    	ROLW $1, (R11)                          // 6641d103
    	ROLW $1, DX                             // 66d1c2
    	ROLW $1, R11                            // 6641d1c3
    	ROLW CL, (BX)                           // 66d303
    	ROLW CL, (R11)                          // 6641d303
    	ROLW CL, DX                             // 66d3c2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Oct 08 21:38:44 UTC 2021
    - 581.9K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/AMD64Ops.go

    		{name: "ROLQ", argLength: 2, reg: gp21shift, asm: "ROLQ", resultInArg0: true, clobberFlags: true},
    		{name: "ROLL", argLength: 2, reg: gp21shift, asm: "ROLL", resultInArg0: true, clobberFlags: true},
    		{name: "ROLW", argLength: 2, reg: gp21shift, asm: "ROLW", resultInArg0: true, clobberFlags: true},
    		{name: "ROLB", argLength: 2, reg: gp21shift, asm: "ROLB", resultInArg0: true, clobberFlags: true},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Aug 04 16:40:24 UTC 2023
    - 98K bytes
    - Viewed (1)
  4. src/cmd/compile/internal/ssa/rewriteRISCV64.go

    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (ROLW x (MOVDconst [val]))
    	// result: (RORIW [int64(int8(-val)&31)] x)
    	for {
    		x := v_0
    		if v_1.Op != OpRISCV64MOVDconst {
    			break
    		}
    		val := auxIntToInt64(v_1.AuxInt)
    		v.reset(OpRISCV64RORIW)
    		v.AuxInt = int64ToAuxInt(int64(int8(-val) & 31))
    		v.AddArg(x)
    		return true
    	}
    	// match: (ROLW x (NEG y))
    	// result: (RORW x y)
    	for {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 205.1K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/rewriteAMD64.go

    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (ROLW x (NEGQ y))
    	// result: (RORW x y)
    	for {
    		x := v_0
    		if v_1.Op != OpAMD64NEGQ {
    			break
    		}
    		y := v_1.Args[0]
    		v.reset(OpAMD64RORW)
    		v.AddArg2(x, y)
    		return true
    	}
    	// match: (ROLW x (NEGL y))
    	// result: (RORW x y)
    	for {
    		x := v_0
    		if v_1.Op != OpAMD64NEGL {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 712.7K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/rewrite386.go

    			break
    		}
    		x := v_0
    		v.copyOf(x)
    		return true
    	}
    	return false
    }
    func rewriteValue386_Op386ROLW(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (ROLW x (MOVLconst [c]))
    	// result: (ROLWconst [int16(c&15)] x)
    	for {
    		x := v_0
    		if v_1.Op != Op386MOVLconst {
    			break
    		}
    		c := auxIntToInt32(v_1.AuxInt)
    		v.reset(Op386ROLWconst)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 21 21:05:46 UTC 2023
    - 262.4K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/opGen.go

    			inputs: []inputInfo{
    				{1, 2},   // CX
    				{0, 239}, // AX CX DX BX BP SI DI
    			},
    			outputs: []outputInfo{
    				{0, 239}, // AX CX DX BX BP SI DI
    			},
    		},
    	},
    	{
    		name:         "ROLW",
    		argLen:       2,
    		resultInArg0: true,
    		clobberFlags: true,
    		asm:          x86.AROLW,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{1, 2},   // CX
    				{0, 239}, // AX CX DX BX BP SI DI
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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