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Results 11 - 14 of 14 for NEGD (0.09 sec)

  1. src/cmd/compile/internal/ssa/_gen/ARMOps.go

    		// unary ops
    		{name: "MVN", argLength: 1, reg: gp11, asm: "MVN"}, // ^arg0
    
    		{name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"},   // -arg0, float32
    		{name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"},   // -arg0, float64
    		{name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64
    		{name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 24 00:21:13 UTC 2023
    - 41K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/ARM.rules

    (NEGF (MULF x y)) && buildcfg.GOARM.Version >= 6 => (NMULF x y)
    (NEGD (MULD x y)) && buildcfg.GOARM.Version >= 6 => (NMULD x y)
    (MULF (NEGF x) y) && buildcfg.GOARM.Version >= 6 => (NMULF x y)
    (MULD (NEGD x) y) && buildcfg.GOARM.Version >= 6 => (NMULD x y)
    (NMULF (NEGF x) y) => (MULF x y)
    (NMULD (NEGD x) y) => (MULD x y)
    
    // the result will overwrite the addend, since they are in the same register
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 90.1K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/rewriteARM.go

    		v.AuxInt = int32ToAuxInt(c * d)
    		v.AddArg(a)
    		return true
    	}
    	return false
    }
    func rewriteValueARM_OpARMMULD(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (MULD (NEGD x) y)
    	// cond: buildcfg.GOARM.Version >= 6
    	// result: (NMULD x y)
    	for {
    		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
    			if v_0.Op != OpARMNEGD {
    				continue
    			}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 486.8K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/opGen.go

    			},
    			outputs: []outputInfo{
    				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
    			},
    		},
    	},
    	{
    		name:   "NEGD",
    		argLen: 1,
    		asm:    arm.ANEGD,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
    			},
    			outputs: []outputInfo{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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