PUSHW DX                                // 66fff2 or 6652
	POPW AX
	PUSHW R11                               // 6641fff3 or 664153
	POPW AX
	PUSHQ (BX)                              // ff33
	POPQ AX
	PUSHQ (R11)                             // 41ff33
	POPQ AX
	PUSHQ DX                                // fff2 or 52
	POPQ AX
	PUSHQ R11                               // 41fff3 or 4153
	POPQ AX

For example, the sequence to load <code>g</code> and <code>m</code>
using <code>CX</code> looks like this:
</p>

<pre>
#include "go_tls.h"
#include "go_asm.h"
...
get_tls(CX)
MOVL	g(CX), AX     // Move g into AX.
MOVL	g_m(AX), BX   // Move g.m into BX.
</pre>

<p>
The <code>get_tls</code> macro is also defined on <a href="#amd64">amd64</a>.
</p>

<p>
Addressing modes:
</p>

<ul>

<li>

			if tok == scanner.EOF {
				p.errorf("unexpected EOF")
				return "", "", nil, false
			}
			// Split operands on comma. Also, the old syntax on x86 for a "register pair"
			// was AX:DX, for which the new syntax is DX, AX. Note the reordering.
			if tok == '\n' || tok == ';' || (nesting == 0 && (tok == ',' || tok == ':')) {
				if tok == ':' {
					// Remember this location so we can swap the operands below.
					if colon >= 0 {

	VGATHERPF1DPD K2, (R14)(Y29*8)                     // 6292fd42c614ee
	VGATHERPF1DPD K2, (AX)(Y4*1)                       // 62f2fd4ac61420
	VGATHERPF1DPD K2, (BP)(Y10*2)                      // 62b2fd4ac6545500
	VGATHERPF1DPS K3, (DX)(Z10*4)                      // 62b27d4bc61492
	VGATHERPF1DPS K3, (AX)(Z4*1)                       // 62f27d4bc61420
	VGATHERPF1DPS K3, (SP)(Z4*2)                       // 62f27d4bc61464

	V4FMADDSS 7(AX), [X0-X3], K5, X3                   // 62f27f0d9b9807000000 or 62f27f2d9b9807000000 or 62f27f4d9b9807000000
	V4FMADDSS (DI), [X0-X3], K5, X3                    // 62f27f0d9b1f or 62f27f2d9b1f or 62f27f4d9b1f
	V4FMADDSS 7(AX), [X10-X13], K5, X3                 // 62f22f0d9b9807000000 or 62f22f2d9b9807000000 or 62f22f4d9b9807000000
	V4FMADDSS (DI), [X10-X13], K5, X3                  // 62f22f0d9b1f or 62f22f2d9b1f or 62f22f4d9b1f

	VMOVNTDQA 7(AX)(CX*4), Z2                          // 62f27d482a948807000000
	VMOVNTDQA 7(AX)(CX*1), Z2                          // 62f27d482a940807000000
	VMOVNTDQA 7(AX)(CX*4), Z21                         // 62e27d482aac8807000000
	VMOVNTDQA 7(AX)(CX*1), Z21                         // 62e27d482aac0807000000
	VMOVNTPD Y26, (AX)                                 // 6261fd282b10

	VPMADD52LUQ Z13, Z21, K7, Z8                       // 6252d547b4c5
	VPMADD52LUQ 7(AX), Z21, K7, Z8                     // 6272d547b48007000000
	VPMADD52LUQ (DI), Z21, K7, Z8                      // 6272d547b407
	VPMADD52LUQ Z16, Z5, K7, Z8                        // 6232d54fb4c0
	VPMADD52LUQ Z13, Z5, K7, Z8                        // 6252d54fb4c5
	VPMADD52LUQ 7(AX), Z5, K7, Z8                      // 6272d54fb48007000000

	VPDPBUSDS 7(AX)(CX*4), X14, K4, X19                // 62e20d0c519c8807000000
	VPDPBUSDS 7(AX)(CX*1), X14, K4, X19                // 62e20d0c519c0807000000
	VPDPBUSDS X25, X0, K4, X19                         // 62827d0c51d9
	VPDPBUSDS X11, X0, K4, X19                         // 62c27d0c51db
	VPDPBUSDS X17, X0, K4, X19                         // 62a27d0c51d9

	VPOPCNTQ 7(AX)(CX*4), K2, Y1                       // 62f2fd2a558c8807000000
	VPOPCNTQ 7(AX)(CX*1), K2, Y1                       // 62f2fd2a558c0807000000
	VPOPCNTQ Y5, K2, Y27                               // 6262fd2a55dd
	VPOPCNTQ Y17, K2, Y27                              // 6222fd2a55d9
	VPOPCNTQ Y13, K2, Y27                              // 6242fd2a55dd

	VINSERTF64X2 $0, 7(AX)(CX*1), Y30, K4, Y30         // 62638d2418b4080700000000
	VINSERTF64X2 $0, X3, Y16, K4, Y26                  // 6263fd2418d300
	VINSERTF64X2 $0, X26, Y16, K4, Y26                 // 6203fd2418d200
	VINSERTF64X2 $0, X23, Y16, K4, Y26                 // 6223fd2418d700
	VINSERTF64X2 $0, 7(AX)(CX*4), Y16, K4, Y26         // 6263fd241894880700000000