// Returns true if a type is quantized tensor type.
bool IsQuantizedTensorType(Type type);

// Returns true if all operands and results are quantized.
bool IsOpFullyQuantized(Operation* op);

// Returns true iff none among operand and result tensors are quantized.
bool IsOpNotQuantized(Operation* op);

}  // namespace quant
}  // namespace mlir

    for (auto operand_and_idx : llvm::enumerate(fetch.getOperands())) {
      Value operand = operand_and_idx.value();
      if (mlir::isa<mlir::tf_executor::ControlType>(operand.getType())) break;

      auto* dst_node = returns_[fetch][operand_and_idx.index()];
      TF_RETURN_IF_ERROR(AddEdgeBetweenNodes(operand, dst_node, 0));
    }

    return absl::OkStatus();
  }

    for (auto operand_and_idx : llvm::enumerate(fetch.getOperands())) {
      Value operand = operand_and_idx.value();
      if (mlir::isa<mlir::tf_executor::ControlType>(operand.getType())) break;

      auto* dst_node = returns_[fetch][operand_and_idx.index()];
      TF_RETURN_IF_ERROR(AddEdgeBetweenNodes(operand, dst_node, 0));
    }

    return absl::OkStatus();
  }

    Example:
      %device_tensor = gpurt.transfer_to_device %cpu_tensor
  }];

  let arguments = (ins TFTensorType);
  let results = (outs TFTensorType);
  let assemblyFormat = "operands attr-dict";
}

// TODO(b/260267885): We may add a device argument when we want to support
// GPU MIG.
def TransferFromDeviceOp: Gpu_Op<"transfer_from_device"> {
  let summary = "Transfer a tensor from device.";

	// 2
	// 4
	// 8
	// 16
}

func ExampleFloat_Cmp() {
	inf := math.Inf(1)
	zero := 0.0

	operands := []float64{-inf, -1.2, -zero, 0, +1.2, +inf}

	fmt.Println("   x     y  cmp")
	fmt.Println("---------------")
	for _, x64 := range operands {
		x := big.NewFloat(x64)
		for _, y64 := range operands {
			y := big.NewFloat(y64)
			fmt.Printf("%4g  %4g  %3d\n", x, y, x.Cmp(y))
		}
		fmt.Println()
	}

	VMOV	V8.D[0], V12.S[1]                                // ERROR "operand mismatch"
	VMOV	V8.D[0], V12.H[1]                                // ERROR "operand mismatch"
	VMOV	V8.D[0], V12.B[1]                                // ERROR "operand mismatch"
	VMOV	V8.S[0], V12.H[1]                                // ERROR "operand mismatch"
	VMOV	V8.S[0], V12.B[1]                                // ERROR "operand mismatch"

// TODO(fengliuai): supports a configurable accumulator bit width.
template <int Bias, int... Operands>
class AccumulatorUniformScale {
 public:
  template <typename ConcreteType>
  class Impl
      : public QuantizationSpecTraitBase<
            ConcreteType, AccumulatorUniformScale<Bias, Operands...>::Impl> {
   public:
    // Whether the index-th operand is a bias.
    static bool IsBias(int index) { return index == Bias; }

<h2 id="Expressions">Expressions</h2>

<p>
An expression specifies the computation of a value by applying
operators and functions to operands.
</p>

<h3 id="Operands">Operands</h3>

<p>
Operands denote the elementary values in an expression. An operand may be a
literal, a (possibly <a href="#Qualified_identifiers">qualified</a>)
non-<a href="#Blank_identifier">blank</a> identifier denoting a

  let description = [{
    cond: The boolean to control whether the first iteration should be
      executed.
    operands: The arguments to the first iteration.
    results: The results of the last iteration. The number and types of results
      excluding the last one are the same as the number and types of operands. The
      last element of results is an I1 value that is false.

// quantizable unit.
message StaticRangePtq {
  // Operand index -> QuantizedType mapping. Operands that are not specified
  // here will be quantized with best effort.
  map<int32, QuantizedType> input_quantized_types = 1;
}

message WeightOnlyPtq {
  // Operand index -> QuantizedType mapping. Operands that are not specified
  // here will be quantized with best effort.