}

			if v.reg.clobbers > 0 {
				fmt.Fprintf(w, "clobbers: %d,%s\n", v.reg.clobbers, a.regMaskComment(v.reg.clobbers))
			}

			// reg outputs
			s = s[:0]
			for i, r := range v.reg.outputs {
				s = append(s, intPair{countRegs(r), i})
			}
			if len(s) > 0 {
				sort.Sort(byKey(s))
				fmt.Fprintln(w, "outputs: []outputInfo{")
				for _, p := range s {
					r := v.reg.outputs[p.val]

// SYSREG_END is the last item in the automatically generated system register
// declaration, and it is defined in the sysRegEnc.go file.
// Define the special register after REG_SPECIAL, the first value of it should be
// REG_{name} = SYSREG_END + iota.
const (
	REG_SPECIAL = obj.RBaseARM64 + 1<<12
)

// Register assignments:
//
// compiler allocates R0 up as temps
// compiler allocates register variables R7-R25

	REGCTXT      = REG_DX
	REGENTRYTMP0 = REG_R12     // scratch register available at function entry in ABIInternal
	REGENTRYTMP1 = REG_R13     // scratch register available at function entry in ABIInternal
	REGG         = REG_R14     // g register in ABIInternal
	REGEXT       = REG_R15     // compiler allocates external registers R15 down
	FREGMIN      = REG_X0 + 5  // first register variable

	C_AND0CON
	C_ADDCON // -0x800 <= v < 0
	C_ANDCON // 0 < v <= 0xFFF
	C_LCON   // other 32
	C_DCON   // other 64 (could subdivide further)
	C_SACON  // $n(REG) where n <= int12
	C_SECON
	C_LACON // $n(REG) where int12 < n <= int32
	C_LECON
	C_DACON // $n(REG) where int32 < n
	C_STCON // $tlsvar
	C_SBRA
	C_LBRA
	C_SAUTO
	C_LAUTO
	C_SEXT
	C_LEXT
	C_ZOREG
	C_SOREG
	C_LOREG
	C_GOK

		return true
	}
	return false
}

// IsARMBFX reports whether the op (as defined by an arm.A* constant) is one the
// BFX-like instructions which are in the form of "op $width, $LSB, (Reg,) Reg".
func IsARMBFX(op obj.As) bool {
	switch op {
	case arm.ABFX, arm.ABFXU, arm.ABFC, arm.ABFI:
		return true
	}
	return false
}

zero512setup:  // setup for dcbz loop
	CMP  R4, $512   // check if at least 512
	BLT  remain
	SRD  $9, R4, R8 // loop count for 512 chunks
	MOVD R8, CTR    // set up counter
	MOVD $128, R9   // index regs for 128 bytes
	MOVD $256, R10
	MOVD $384, R11
	PCALIGN $16
zero512:
	DCBZ (R3+R0)        // clear first chunk
	DCBZ (R3+R9)        // clear second chunk
	DCBZ (R3+R10)       // clear third chunk

	memRegistry.XdsUpdater = server.Discovery
	memRegistry.ClusterID = clusterID

	reg := serviceregistry.Simple{
		ClusterID:           clusterID,
		ProviderID:          provider.Mock,
		DiscoveryController: memRegistry,
	}
	server.Env().ServiceDiscovery.(*aggregate.Controller).AddRegistry(reg)

	gws := make([]*meshconfig.Network_IstioNetworkGateway, 0)
	for _, gatewayIP := range gatewaysIP {

			continue
		}
		argRegs = intArgRegs
		unlock(&finlock)
		if raceenabled {
			racefingo()
		}
		for fb != nil {
			for i := fb.cnt; i > 0; i-- {
				f := &fb.fin[i-1]

				var regs abi.RegArgs
				// The args may be passed in registers or on stack. Even for
				// the register case, we still need the spill slots.
				// TODO: revisit if we remove spill slots.
				//

//		On ARM64:
//			offset = (reg&31)<<16 | shifttype<<22 | (count&63)<<10
//			shifttype = 0, 1, 2 for <<, >>, ->
//
//	(reg, reg)
//		A destination register pair. When used as the last argument of an instruction,
//		this form makes clear that both registers are destinations.
//		Encoding:
//			type = TYPE_REGREG
//			reg = first register
//			offset = second register
//
//	[reg, reg, reg-reg]

		return "H"
	case ARNG_S:
		return "S"
	case ARNG_D:
		return "D"
	case ARNG_1Q:
		return "Q1"
	default:
		return ""
	}
}

func rconv(r int) string {
	ext := (r >> 5) & 7
	if r == REGG {
		return "g"
	}
	switch {
	case REG_R0 <= r && r <= REG_R30:
		return fmt.Sprintf("R%d", r-REG_R0)
	case r == REG_R31:
		return "ZR"
	case REG_F0 <= r && r <= REG_F31: