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CHANGELOG/CHANGELOG-1.26.md
### Bug or Regression - Add DisruptionTarget condition to the pod preempted by Kubelet to make room for a critical pod ([#118221](https://github.com/kubernetes/kubernetes/pull/118221), [@mimowo](https://github.com/mimowo)) [SIG Node and Testing]
Registered: Fri Dec 26 09:05:12 UTC 2025 - Last Modified: Thu Mar 14 16:24:51 UTC 2024 - 425.7K bytes - Viewed (0) -
lib/fips140/v1.0.0-c2097c7c.zip
c2 rr4 := r4.lo&maskLow51Bits + c3 // Now all coefficients fit into 64-bit registers but are still too large to // be passed around as an Element. We therefore do one last carry chain, // where the carries will be small enough to fit in the wiggle room above 2⁵¹. *v = Element{rr0, rr1, rr2, rr3, rr4} v.carryPropagate() } func feSquareGeneric(v, a *Element) { l0 := a.l0 l1 := a.l1 l2 := a.l2 l3 := a.l3 l4 := a.l4 // Squaring works precisely like multiplication above, but thanks to its // symmetry...
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Sep 25 19:53:19 UTC 2025 - 642.7K bytes - Viewed (0) -
lib/fips140/v1.1.0-rc1.zip
c2 rr4 := r4.lo&maskLow51Bits + c3 // Now all coefficients fit into 64-bit registers but are still too large to // be passed around as an Element. We therefore do one last carry chain, // where the carries will be small enough to fit in the wiggle room above 2⁵¹. v.l0 = rr0&maskLow51Bits + mul19(rr4>>51) v.l1 = rr1&maskLow51Bits + rr0>>51 v.l2 = rr2&maskLow51Bits + rr1>>51 v.l3 = rr3&maskLow51Bits + rr2>>51 v.l4 = rr4&maskLow51Bits + rr3>>51 } func feSquareGeneric(v, a *Element) { l0 := a.l0 l1 :=...
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Dec 11 16:27:41 UTC 2025 - 663K bytes - Viewed (0)