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Results 1 - 6 of 6 for srl (0.04 sec)

  1. src/cmd/asm/internal/asm/testdata/arm.s

    	SRL.S	$31, R5, R6          // a56fb0e1
    	SRL	$14, R5              // 2557a0e1
    	SRL	$15, R5              // a557a0e1
    	SRL	$30, R5              // 255fa0e1
    	SRL	$31, R5              // a55fa0e1
    	SRL.S	$14, R5              // 2557b0e1
    	SRL.S	$15, R5              // a557b0e1
    	SRL.S	$30, R5              // 255fb0e1
    	SRL.S	$31, R5              // a55fb0e1
    	SRL	R5, R6, R7           // 3675a0e1
    	SRL.S	R5, R6, R7           // 3675b0e1
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 69K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/mips64.s

    	SLLV	R10, R22, R21	// 0156a814
    	SRL	R27, R6, R17	// 03668806
    	SRLV	R27, R6, R17	// 03668816
    	SRA	R11, R19, R20	// 0173a007
    	SRAV	R20, R19, R19	// 02939817
    	ROTR	R19, R18, R20	// 0272a046
    	ROTRV	R9, R13, R16	// 012d8056
    
    //	LSHW rreg ',' rreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	SLL	R1, R2		// 00221004
    	SLLV	R10, R22	// 0156b014
    	SRL	R27, R6   	// 03663006
    	SRLV	R27, R6   	// 03663016
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	ADD	R4, R5			// a5101000
    	ADDV	R4, R5			// a5901000
    	AND	R4, R5			// a5901400
    	NEGW	R4, R5			// 05101100
    	NEGV	R4, R5			// 05901100
    	SLL	R4, R5			// a5101700
    	SLL	R4, R5, R6		// a6101700
    	SRL	R4, R5			// a5901700
    	SRL	R4, R5, R6	 	// a6901700
    	SRA	R4, R5			// a5101800
    	SRA	R4, R5, R6	 	// a6101800
    	ROTR	R4, R5			// a5101b00
    	ROTR	R4, R5, R6		// a6101b00
    	SLLV	R4, R5			// a5901800
    	SLLV	R4, R5, R6		// a6901800
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Thu Sep 04 19:24:25 UTC 2025
    - 35.5K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/riscv64.s

    	LUI	$524287, X15				// b7f7ff7f
    
    	SLL	X6, X5, X7				// b3936200
    	SLL	X5, X6					// 33135300
    	SLL	$1, X5, X6				// 13931200
    	SLL	$1, X5					// 93921200
    	SRL	X6, X5, X7				// b3d36200
    	SRL	X5, X6					// 33535300
    	SRL	$1, X5, X6				// 13d31200
    	SRL	$1, X5					// 93d21200
    
    	SUB	X6, X5, X7				// b3836240
    	SUB	X5, X6					// 33035340
    	SUB	$-2047, X5, X6				// 1383f27f
    	SUB	$2048, X5, X6				// 13830280
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed May 21 14:19:19 UTC 2025
    - 49.1K bytes
    - Viewed (0)
  5. fess-crawler/src/main/resources/org/codelibs/fess/crawler/mime/tika-mimetypes.xml

      <mime-type type="application/sereal">
        <_comment>Sereal binary serialization format</_comment>
        <tika:link>https://github.com/Sereal/Sereal/blob/master/sereal_spec.pod</tika:link>
        <glob pattern="*.srl"/>
      </mime-type>
      <mime-type type="application/sereal;version=1">
        <sub-class-of type="application/sereal"/>
        <magic priority="50">
          <match value="0x6C72733D" type="little32" offset="0">
    Registered: Sun Sep 21 03:50:09 UTC 2025
    - Last Modified: Thu Mar 13 08:18:01 UTC 2025
    - 320.1K bytes
    - Viewed (1)
  6. lib/fips140/v1.0.0.zip

    (((index-2)&0xf)*4)(R3), REGTMP4; \ MOVW (((index-15)&0xf)*4)(R3), REGTMP1; \ MOVW (((index-7)&0xf)*4)(R3), REGTMP; \ MOVW REGTMP4, REGTMP2; \ MOVW REGTMP4, REGTMP3; \ ROTR $17, REGTMP4; \ ROTR $19, REGTMP2; \ SRL $10, REGTMP3; \ XOR REGTMP2, REGTMP4; \ XOR REGTMP3, REGTMP4; \ ROTR $7, REGTMP1, REGTMP5; \ SRL $3, REGTMP1, REGTMP3; \ ROTR $18, REGTMP1, REGTMP2; \ ADD REGTMP, REGTMP4; \ MOVW (((index-16)&0xf)*4)(R3), REGTMP; \ XOR REGTMP3, REGTMP5; \ XOR REGTMP2, REGTMP5; \ ADD REGTMP, REGTMP5; \ ADD REGTMP5,...
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Jan 29 15:10:35 UTC 2025
    - 635K bytes
    - Viewed (0)
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