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Results 1 - 10 of 41 for sreg (0.08 sec)

  1. src/cmd/asm/internal/asm/testdata/mips64.s

    //	LFADD freg ',' freg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	ADDD	F1, F2
    
    //	LFADD freg ',' freg ',' freg
    //	{
    //		outcode(int($1), &$2, int($4.Reg), &$6);
    //	}
    	ADDD	F1, F2, F3
    
    //	LFCMP freg ',' freg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	CMPEQD	F1, F2
    
    
    //
    // WORD
    //
    	WORD	$1	// 00000001
    	NOOP		// 00000000
    	SYNC		// 0000000f
    
    //
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
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  2. src/cmd/asm/internal/asm/testdata/mips.s

    	//	}
    	ADD	$4, R1
    
    	//	LMUL rreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	MUL	R1, R2
    
    	//	LSHW rreg ',' sreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, int($4), &$6);
    	//	}
    	SLL	R1, R2, R3
    
    	//	LSHW rreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	SLL	R1, R2
    
    	//	LSHW imm ',' sreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, int($4), &$6);
    	//	}
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 6.7K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/arm.s

    // MULL r1,r2,(hi,lo)
    //
    //	LTYPEM cond reg ',' reg ',' regreg
    //	{
    //		outcode($1, $2, &$3, int32($5.Reg), &$7);
    //	}
    	MULL	R1, R2, (R3,R4)
    
    //
    // MULA r1,r2,r3,r4: (r1*r2+r3) & 0xffffffff . r4
    // MULAW{T,B} r1,r2,r3,r4
    //
    //	LTYPEN cond reg ',' reg ',' reg ',' spreg
    //	{
    //		$7.Type = obj.TYPE_REGREG2;
    //		$7.Offset = int64($9);
    //		outcode($1, $2, &$3, int32($5.Reg), &$7);
    //	}
    	MULAWT	R1, R2, R3, R4
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 69K bytes
    - Viewed (0)
  4. build-logic/documentation/src/main/groovy/gradlebuild/docs/dsl/docbook/PropertyDetailRenderer.java

                for (ExtraAttributeDoc attributeDoc : propertyDoc.getAdditionalValues()) {
                    Element seg = document.createElement("seg");
                    seglistitem.appendChild(seg);
                    for (Node node : attributeDoc.getValue()) {
                        seg.appendChild(document.importNode(node, true));
                    }
                }
            }
        }
    
    Registered: Wed Nov 06 11:36:14 UTC 2024
    - Last Modified: Wed Dec 09 08:14:05 UTC 2020
    - 3.5K bytes
    - Viewed (0)
  5. tests/test_router_prefix_with_template.py

    
    app.include_router(router, prefix="/{segment}")
    
    
    client = TestClient(app)
    
    
    def test_get():
        response = client.get("/seg/users/foo")
        assert response.status_code == 200, response.text
    Registered: Sun Nov 03 07:19:11 UTC 2024
    - Last Modified: Wed Apr 08 04:37:38 UTC 2020
    - 484 bytes
    - Viewed (0)
  6. licenses/github.com/gregjones/httpcache/LICENSE.txt

    Copyright © 2012 Greg Jones (greg******@****.***)
    
    Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the “Software”), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
    
    Registered: Wed Nov 06 22:53:10 UTC 2024
    - Last Modified: Sat Oct 26 02:47:39 UTC 2019
    - 1.1K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/arch/arm64.go

    		}
    	} else if reg <= arm64.REG_V31 && reg >= arm64.REG_V0 {
    		switch ext {
    		case "B8":
    			if isIndex {
    				return errors.New("invalid register extension")
    			}
    			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8B & 15) << 5)
    		case "B16":
    			if isIndex {
    				return errors.New("invalid register extension")
    			}
    			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_16B & 15) << 5)
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Thu Sep 29 09:04:58 UTC 2022
    - 10.4K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/parse.go

    	// Expect (SB), (FP), (PC), or (SP)
    	p.get('(')
    	reg := p.get(scanner.Ident).String()
    	p.get(')')
    	p.setPseudoRegister(a, reg, isStatic, prefix)
    }
    
    // setPseudoRegister sets the NAME field of addr for a pseudo-register reference such as (SB).
    func (p *Parser) setPseudoRegister(addr *obj.Addr, reg string, isStatic bool, prefix rune) {
    	if addr.Reg != 0 {
    		p.errorf("internal error: reg %s already set in pseudo", reg)
    	}
    	switch reg {
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Sep 04 18:16:59 UTC 2024
    - 36.9K bytes
    - Viewed (0)
  9. src/cmd/asm/internal/asm/asm.go

    			// the CR bit.
    			prog.Reg = a[1].Reg
    			if a[1].Type != obj.TYPE_REG {
    				// The CR bit is represented as a constant 0-31. Convert it to a Reg.
    				c := p.getConstant(prog, op, &a[1])
    				reg, success := ppc64.ConstantToCRbit(c)
    				if !success {
    					p.errorf("invalid CR bit register number %d", c)
    				}
    				prog.Reg = reg
    			}
    			break
    		}
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Mon Oct 21 14:11:44 UTC 2024
    - 25.5K bytes
    - Viewed (0)
  10. src/archive/tar/testdata/ustar-file-reg.tar

    Joe Tsai <******@****.***> 1443691829 -0700
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Fri Nov 06 04:31:26 UTC 2015
    - 1.5K bytes
    - Viewed (0)
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