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Results 1 - 10 of 38 for r2 (0.01 sec)
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src/cmd/asm/internal/asm/testdata/arm64.s
FMOVS F1, 0x44332211(R2) // FMOVS F1, 1144201745(R2) FMOVD F1, 0x1007000(R2) // FMOVD F1, 16805888(R2) FMOVD F1, 0x44332211(R2) // FMOVD F1, 1144201745(R2) MOVB 0x1000000(R1), R2 // MOVB 16777216(R1), R2 MOVB 0x44332211(R1), R2 // MOVB 1144201745(R1), R2 MOVH 0x1000000(R1), R2 // MOVH 16777216(R1), R2 MOVH 0x44332211(R1), R2 // MOVH 1144201745(R1), R2 MOVW 0x1000000(R1), R2 // MOVW 16777216(R1), R2
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Jul 24 18:45:14 UTC 2024 - 95.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
.github/workflows/update-rbe.yml
# TF 2.9 map sigbuild-r2.9 2.9-python3.9 map sigbuild-r2.9-python3.8 2.9-python3.8 map sigbuild-r2.9-python3.9 2.9-python3.9 map sigbuild-r2.9-python3.10 2.9-python3.10 # TF 2.10 map sigbuild-r2.10 2.10-python3.9 map sigbuild-r2.10-python3.8 2.10-python3.8 map sigbuild-r2.10-python3.9 2.10-python3.9 map sigbuild-r2.10-python3.10 2.10-python3.10 # TF 2.11
Registered: Tue Nov 05 12:39:12 UTC 2024 - Last Modified: Fri Nov 01 08:40:10 UTC 2024 - 7.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/armerror.s
BFX $-2, $4, R2, R3 // ERROR "wrong width or LSB" BFXU $4, R2, R5, R2 // ERROR "missing or wrong LSB" BFXU $4, R2, R5 // ERROR "missing or wrong LSB" BFC $12, $8, R2, R3 // ERROR "illegal combination" MOVB R0>>8, R2 // ERROR "illegal shift" MOVH R0<<16, R2 // ERROR "illegal shift" MOVBS R0->8, R2 // ERROR "illegal shift" MOVHS R0<<24, R2 // ERROR "illegal shift"
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Oct 23 15:18:14 UTC 2024 - 14.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// } MOVW R1, R2 MOVW LO, R1 MOVW HI, R1 MOVW R1, LO MOVW R1, HI MOVW R1, R2 MOVW LO, R1 MOVW HI, R1 MOVW R1, LO MOVW R1, HI // LMOVW addr ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW foo<>+3(SB), R2 MOVW 16(R1), R2 MOVW (R1), R2 MOVW foo<>+3(SB), R2 MOVW 16(R1), R2 MOVW (R1), R2 LL (R1), R2 // LMOVB rreg ',' rreg // {
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
AND R0->R1, R2, R3 // 503102e0 AND R0@>R1, R2, R3 // 703102e0 AND.S R0<<R1, R2, R3 // 103112e0 AND.S R0>>R1, R2, R3 // 303112e0 AND.S R0->R1, R2, R3 // 503112e0 AND.S R0@>R1, R2, R3 // 703112e0 AND R0<<R1, R2 // 102102e0 AND R0>>R1, R2 // 302102e0 AND R0->R1, R2 // 502102e0 AND R0@>R1, R2 // 702102e0 AND.S R0<<R1, R2 // 102112e0
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
MOVW R1, 4095(R2)(R3) // 50132fff MOVW R1, 4096(R2)(R3) // e31320000150 MOVWZ R1, 4095(R2)(R3) // 50132fff MOVWZ R1, 4096(R2)(R3) // e31320000150 MOVH R1, 4095(R2)(R3) // 40132fff MOVHZ R1, 4095(R2)(R3) // 40132fff MOVH R1, 4096(R2)(R3) // e31320000170 MOVHZ R1, 4096(R2)(R3) // e31320000170 MOVB R1, 4095(R2)(R3) // 42132fff
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Sep 18 15:49:24 UTC 2024 - 22.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64_p10.s
SETBC CR2EQ, R2 // 7c4a0300 SETBCR CR2LT, R2 // 7c480340 SETNBC CR2GT, R2 // 7c490380 SETNBCR CR6SO, R2 // 7c5b03c0 STXVP VS6, 12352(R5) // 18c53041 STXVPX VS22, (R1)(R2) // 7ec20b9a STXVRBX VS2, (R1)(R2) // 7c42091a STXVRDX VS2, (R1)(R2) // 7c4209da
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Thu Mar 23 20:52:57 UTC 2023 - 14.3K bytes - Viewed (0) -
cmd/dummy-data-generator_test.go
func TestCmpReaders(t *testing.T) { { r1 := bytes.NewReader([]byte("abc")) r2 := bytes.NewReader([]byte("abc")) ok, msg := cmpReaders(r1, r2) if !(ok && msg == "") { t.Fatalf("unexpected") } } { r1 := bytes.NewReader([]byte("abc")) r2 := bytes.NewReader([]byte("abcd")) ok, _ := cmpReaders(r1, r2) if ok { t.Fatalf("unexpected") } }
Registered: Sun Nov 03 19:28:11 UTC 2024 - Last Modified: Tue Jul 02 15:13:05 UTC 2024 - 4.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
JAL foo(SB) // CALL foo(SB) BEQ R1, 2(PC) JMP foo(SB) CALL foo(SB) RET foo(SB) // unary operation NEGW R1, R2 // 00011023 NEGV R1, R2 // 0001102f WSBH R1, R2 // 7c0110a0 DSBH R1, R2 // 7c0110a4 DSHD R1, R2 // 7c011164 SEB R1, R2 // 7c011420 SEH R1, R2 // 7c011620 RET // MSA VMOVI VMOVB $511, W0 // 7b0ff807 VMOVH $24, W23 // 7b20c5c7
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0)