VSPLTISB $0, ZER \ VSUBCUQ T0, PL, CAR1 \ // VSCBIQ VSUBUQM T0, PL, TT0 \ VSUBECUQ T1, PH, CAR1, CAR2 \ // VSBCBIQ VSUBEUQM T1, PH, CAR1, TT1 \ // VSBIQ VSUBEUQM T2, ZER, CAR2, SEL1 \ \ VSEL TT0, T0, SEL1, T0 \ VSEL TT1, T1, SEL1, T1 #define p256HalfInternal(T1, T0, X1, X0) \ VSPLTISB $0, ZER \ VSUBEUQM ZER, ZER, X0, SEL1 \ \ VADDCUQ X0, PL, CAR1 \ VADDUQM X0, PL, T0 \ VADDECUQ X1, PH, CAR1, T2 \ VADDEUQM X1, PH, CAR1, T1 \ \ VSEL T0, X0, SEL1, T0 \ VSEL T1, X1, SEL1, T1 \ VSEL T2, ZER, SEL1, T2...