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Results 1 - 6 of 6 for fpscr (0.02 sec)

  1. src/cmd/asm/internal/asm/testdata/mips64.s

    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	MOVD	F1, foo<>+3(SB)
    	MOVD	F1, 16(R2)
    	MOVD	F1, (R2)
    
    //
    // floating point status
    //
    //	LMOVW fpscr ',' freg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	MOVW	FCR31, R1 // 4441f800
    
    //	LMOVW freg ','  fpscr
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	MOVW	R1, FCR31 // 44c1f800
    
    //	LMOVW rreg ',' mreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/mips.s

    	//	}
    	MOVD	F1, foo<>+3(SB)
    	MOVD	F1, 16(R2)
    	MOVD	F1, (R2)
    
    	//
    	// floating point status
    	//
    	//	LMOVW fpscr ',' freg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	MOVW	FCR0, R1
    
    	//	LMOVW freg ','  fpscr
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	MOVW	R1, FCR0
    
    	//	LMOVW rreg ',' mreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 6.7K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/arch/arch.go

    		register[obj.Rconv(i)] = int16(i)
    	}
    	register["CR"] = ppc64.REG_CR
    	register["XER"] = ppc64.REG_XER
    	register["LR"] = ppc64.REG_LR
    	register["CTR"] = ppc64.REG_CTR
    	register["FPSCR"] = ppc64.REG_FPSCR
    	register["MSR"] = ppc64.REG_MSR
    	// Pseudo-registers.
    	register["SB"] = RSB
    	register["FP"] = RFP
    	register["PC"] = RPC
    	// Avoid unintentionally clobbering g using R30.
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Thu Nov 07 02:20:14 UTC 2024
    - 21.7K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/armerror.s

    	MOVM.DB	[R0-R4], 4(R1)     // ERROR "offset must be zero"
    	MOVW	CPSR, FPSR         // ERROR "illegal combination"
    	MOVW	FPSR, CPSR         // ERROR "illegal combination"
    	MOVW	CPSR, errors(SB)   // ERROR "illegal combination"
    	MOVW	errors(SB), CPSR   // ERROR "illegal combination"
    	MOVW	FPSR, errors(SB)   // ERROR "illegal combination"
    	MOVW	errors(SB), FPSR   // ERROR "illegal combination"
    	MOVW	F0, errors(SB)     // ERROR "illegal combination"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Oct 23 15:18:14 UTC 2024
    - 14.5K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/arm64.s

    	MRS	FAR_EL1, R9                        // 096038d5
    	MSR	R25, FAR_EL1                       // 196018d5
    	MRS	FPCR, R1                           // 01443bd5
    	MSR	R27, FPCR                          // 1b441bd5
    	MRS	FPSR, R5                           // 25443bd5
    	MSR	R15, FPSR                          // 2f441bd5
    	MRS	ID_AA64AFR0_EL1, R19               // 930538d5
    	MRS	ID_AA64AFR1_EL1, R24               // b80538d5
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 95.3K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/asm/testdata/arm.s

    	MOVW	$0xff000000, CPSR    // MOVW $4278190080, CPSR    // fff42ce3
    	MOVW	FPSR, R9                                          // 109af1ee
    	MOVW	FPSR, g                                           // 10aaf1ee
    	MOVW	R9, FPSR                                          // 109ae1ee
    	MOVW	g, FPSR                                           // 10aae1ee
    	MOVW	R0>>28(R1), R2                                    // 202e91e7
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 69K bytes
    - Viewed (0)
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