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Results 1 - 6 of 6 for XlaRngBitGenerator (0.18 sec)
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tensorflow/compiler/jit/xla_ops_on_regular_devices.cc
REGISTER_KERNEL_BUILDER(Name("XlaEinsum").Device(DEVICE), \ XlaCompileOnDemandOp); \ REGISTER_KERNEL_BUILDER(Name("XlaRngBitGenerator") \ .HostMemory("algorithm") \ .HostMemory("shape") \
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Aug 19 19:55:14 UTC 2022 - 8.8K bytes - Viewed (0) -
tensorflow/compiler/jit/compilability_check_util.cc
"XlaReduce", "XlaReduceWindow", "XlaReplicaId", "XlaRngBitGenerator", "XlaScatter", "XlaSelectAndScatter", "XlaSelfAdjointEig",
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Mar 12 06:33:33 UTC 2024 - 30.3K bytes - Viewed (0) -
tensorflow/compiler/jit/mark_for_compilation_pass.cc
"XlaRecv", "XlaReduce", "XlaReducePrecision", "XlaReduceScatter", "XlaReduceWindow", "XlaRemoveDynamicDimensionSize", "XlaReplicaId", "XlaRngBitGenerator", "XlaScatter", "XlaSelectAndScatter", "XlaSelfAdjointEig", "XlaSend", "XlaSetBound", "XlaSetDynamicDimensionSize", "XlaSharding", "XlaSort",
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Feb 21 12:19:41 UTC 2024 - 85.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/tf2xla/tests/legalize-tf.mlir
%output = "tf.XlaSort"(%input): (tensor<2x3xi64>) -> (tensor<2x3xi64>) func.return %output : tensor<2x3xi64> } //===----------------------------------------------------------------------===// // tf.XlaRngBitGenerator legalization //===----------------------------------------------------------------------===// // CHECK-LABEL: @xla_rng_bit_generator // CHECK-SAME: %[[STATE:.*]]: tensor<2xui64>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon May 06 18:46:23 UTC 2024 - 335.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tf2xla/transforms/legalize_tf.cc
return xla::RandomAlgorithm::RNG_THREE_FRY; } else if (alg == tensorflow::RNG_ALG_AUTO_SELECT) { return xla::RandomAlgorithm::RNG_DEFAULT; } return std::nullopt; } // Converts tf.XlaRngBitGenerator op to mhlo.RngBitGenerator op. class ConvertXlaRngBitGeneratorOp : public OpRewritePattern<TF::XlaRngBitGeneratorOp> { public: using OpRewritePattern::OpRewritePattern;
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 11 20:00:43 UTC 2024 - 291.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/ir/tf_generated_ops.td
TF_Int32Tensor:$id ); // Constant folding is disabled for this op as it is a runtime op and can't // constant folded at the compile time. } def TF_XlaRngBitGeneratorOp : TF_Op<"XlaRngBitGenerator", [Pure]> { let summary = "Stateless PRNG bit generator."; let description = [{ Wraps the XLA RngBitGenerator operator, documented at
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 11 23:24:08 UTC 2024 - 793K bytes - Viewed (0)