ADDSD (R11), X2                         // f2410f5813
	ADDSD X2, X2                            // f20f58d2
	ADDSD X11, X2                           // f2410f58d3
	ADDSD (BX), X11                         // f2440f581b
	ADDSD (R11), X11                        // f2450f581b
	ADDSD X2, X11                           // f2440f58da
	ADDSD X11, X11                          // f2450f58db

	SHA256MSG1 X2, X2        // 0f38ccd2
	SHA256MSG1 X11, X2       // 410f38ccd3
	SHA256MSG1 (BX), X11     // 440f38cc1b
	SHA256MSG1 (R11), X11    // 450f38cc1b
	SHA256MSG1 X2, X11       // 440f38ccda
	SHA256MSG1 X11, X11      // 450f38ccdb
	SHA256MSG2 (BX), X2      // 0f38cd13
	SHA256MSG2 (R11), X2     // 410f38cd13
	SHA256MSG2 X2, X2        // 0f38cdd2
	SHA256MSG2 X11, X2       // 410f38cdd3

	VRCP28SD X25, X14, K4, X2                          // 62928d0ccbd1
	VRCP28SD X11, X14, K4, X2                          // 62d28d0ccbd3
	VRCP28SD X17, X14, K4, X2                          // 62b28d0ccbd1
	VRCP28SD X25, X0, K4, X2                           // 6292fd0ccbd1
	VRCP28SD X11, X0, K4, X2                           // 62d2fd0ccbd3
	VRCP28SD X17, X0, K4, X2                           // 62b2fd0ccbd1

	VPGATHERDQ X2, 664(X2*8), X7    // ERROR "mask, index, and destination registers should be distinct"
	VPGATHERDQ X2, 664(X7*8), X2    // ERROR "mask, index, and destination registers should be distinct"
	VPGATHERDQ X7, 664(X2*8), X2    // ERROR "mask, index, and destination registers should be distinct"
	// Non-X0 for Yxr0 should produce an error

		// Test AVX512 suffixes.
		{"VADDPD.A X0, X1, X2", `unknown suffix "A"`},
		{"VADDPD.A.A X0, X1, X2", `unknown suffix "A"; duplicate suffix "A"`},
		{"VADDPD.A.A.A X0, X1, X2", `unknown suffix "A"; duplicate suffix "A"`},
		{"VADDPD.A.B X0, X1, X2", `unknown suffix "A"; unknown suffix "B"`},
		{"VADDPD.Z.A X0, X1, X2", `Z suffix should be the last; unknown suffix "A"`},
		{"VADDPD.Z.Z X0, X1, X2", `Z suffix should be the last; duplicate suffix "Z"`},

	VPSHRDVW X2, X2, K7, X0                            // 62f2ed0f72c2
	VPSHRDVW X31, X2, K7, X0                           // 6292ed0f72c7
	VPSHRDVW X11, X2, K7, X0                           // 62d2ed0f72c3
	VPSHRDVW (AX), X2, K7, X0                          // 62f2ed0f7200
	VPSHRDVW 7(SI), X2, K7, X0                         // 62f2ed0f728607000000
	VPSHRDVW X2, X8, K7, X0                            // 62f2bd0f72c2

	VPDPWSSD X2, X2, K3, X18                           // 62e26d0b52d2
	VPDPWSSD X27, X2, K3, X18                          // 62826d0b52d3
	VPDPWSSD X26, X2, K3, X18                          // 62826d0b52d2
	VPDPWSSD (SI), X2, K3, X18                         // 62e26d0b5216
	VPDPWSSD 7(SI)(DI*2), X2, K3, X18                  // 62e26d0b52947e07000000
	VPDPWSSD X2, X24, K3, X18                          // 62e23d0352d2

	IMULB	DX
	IMULW	DX, BX
	IMULL	R11, R12
	IMULQ	foo+4(SB), R11

// LTYPEXC spec8	{ outcode($1, &$2); }
	CMPPD	X1, X2, 4
	CMPPD	foo+4(SB), X2, 4

// LTYPEX spec9	{ outcode($1, &$2); }
	PINSRW	$4, AX, X2
	PINSRW	$4, foo+4(SB), X2

// LTYPERT spec10	{ outcode($1, &$2); }
	JCS	2(PC)
	RETFL	$4

// Was bug: LOOP is a branch instruction.
	JCS	2(PC)
loop:

	VPERMB -7(DI)(R8*2), X20, K1, X23                  // 62a25d018dbc47f9ffffff
	VPERMB X26, X2, K1, X23                            // 62826d098dfa
	VPERMB X19, X2, K1, X23                            // 62a26d098dfb
	VPERMB X0, X2, K1, X23                             // 62e26d098df8
	VPERMB 7(SI)(DI*4), X2, K1, X23                    // 62e26d098dbcbe07000000
	VPERMB -7(DI)(R8*2), X2, K1, X23                   // 62a26d098dbc47f9ffffff

	VPOPCNTW 99(R15), K3, X23                          // 62c2fd0b54bf63000000
	VPOPCNTW X20, K3, X2                               // 62b2fd0b54d4
	VPOPCNTW X5, K3, X2                                // 62f2fd0b54d5
	VPOPCNTW X25, K3, X2                               // 6292fd0b54d1
	VPOPCNTW (CX), K3, X2                              // 62f2fd0b5411
	VPOPCNTW 99(R15), K3, X2                           // 62d2fd0b549763000000