Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 2 of 2 for VP4DPWSSDS (0.06 sec)

  2. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/avx512enc/avx512_4vnniw.s 

    	VP4DPWSSDS -7(DI)(R8*1), [Z4-Z7], K1, Z0           // 62b25f49538407f9ffffff
	VP4DPWSSDS (SP), [Z4-Z7], K1, Z0                   // 62f25f49530424
	VP4DPWSSDS -7(DI)(R8*1), [Z14-Z17], K1, Z0         // 62b20f49538407f9ffffff
	VP4DPWSSDS (SP), [Z14-Z17], K1, Z0                 // 62f20f49530424
	VP4DPWSSDS -7(DI)(R8*1), [Z24-Z27], K1, Z0         // 62b23f41538407f9ffffff
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue May 22 14:57:15 UTC 2018
    - 1.9K bytes
    - Viewed (0)
  3. github.com/golang/go

    src/cmd/asm/internal/asm/parse.go 

    //
// For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.
// For range of 4 elements, Intel manual uses "+3" notation, for example:
//
//	VP4DPWSSDS zmm1{k1}{z}, zmm2+3, m128
//
// Given asm line:
//
//	VP4DPWSSDS Z5, [Z10-Z13], (AX)
//
// zmm2 is Z10, and Z13 is the only valid value for it (Z10+3).
// Only simple ranges are accepted, like [Z0-Z3].
//
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Sep 04 18:16:59 UTC 2024
    - 36.9K bytes
    - Viewed (0)
Back to top