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Results 1 - 3 of 3 for MSUB (0.02 sec)
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src/cmd/asm/internal/arch/mips.go
mips.ACMPGTF, mips.ACMPGTD: return true } return false } // IsMIPSMUL reports whether the op (as defined by an mips.A* constant) is // one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling. func IsMIPSMUL(op obj.As) bool { switch op { case mips.AMUL, mips.AMULU, mips.AMULV, mips.AMULVU, mips.ADIV, mips.ADIVU, mips.ADIVV, mips.ADIVVU,
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Mar 04 19:06:44 UTC 2020 - 1.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
NEGW R1, R2 // 00011023 CLZ R1, R2 // 70221020 CLO R1, R2 // 70221021 WSBH R1, R2 // 7c0110a0 SEB R1, R2 // 7c011420 SEH R1, R2 // 7c011620 // to (Hi, Lo) MADD R2, R1 // 70220000 MSUB R2, R1 // 70220004 MUL R2, R1 // 00220018 // END // // LEND comma // asm doesn't support the trailing comma. // { // outcode(int($1), &nullgen, 0, &nullgen); // }
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
MRS ELR_EL1, R8 // 284038d5 MSR R16, ELR_EL1 // 304018d5 MRS DCZID_EL0, R3 // e3003bd5 MSUBW R1, R1, R12, R5 // 8585011b MSUB R19, R16, R26, R2 // 42c3139b MULW R26, R5, R22 // b67c1a1b MUL R4, R3, R0 // 607c049b MVNW R3@>13, R8 // e837e32a
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0)