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Results 41 - 49 of 49 for isF32 (0.54 sec)
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tensorflow/compiler/mlir/quantization/tensorflow/passes/quantize_composite_functions.cc
return base_function_name.concat("_fn").str(); } bool ContainsFloatResultType(ArrayRef<Type> result_types) { for (auto current_type : result_types) { if (mlir::dyn_cast<TensorType>(current_type).getElementType().isF32()) return true; } return false; } // Unwraps quantization parameters of PartitionedCall ops with quantized // input/outputs that are created from QuantizePass. class QuantizeFunctionPattern
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 54.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/transforms/prepare_tf.cc
if (!epsilon) epsilon = rewriter.getFloatAttr(rewriter.getF32Type(), 0.0001f); if (!(((mlir::isa<::mlir::FloatAttr>(epsilon))) && ((mlir::cast<::mlir::FloatAttr>(epsilon).getType().isF32())))) { return rewriter.notifyMatchFailure( fused_batch_norm_op, [&](::mlir::Diagnostic &diag) { diag << "op 'tf.FusedBatchNormV3' attribute 'epsilon' failed to "
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue May 28 21:49:50 UTC 2024 - 64.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/transforms/lower_static_tensor_list.cc
LogicalResult matchAndRewrite( OpT op, typename OpT::Adaptor adaptor, ConversionPatternRewriter &rewriter) const override { Type dtype = op.getElementDtype(); if (!(dtype.isF16() || dtype.isF32() || dtype.isF64() || dtype.isInteger(1) || dtype.isInteger(8) || dtype.isInteger(16) || dtype.isInteger(32) || dtype.isInteger(64))) { const char *error_info =
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 11 20:00:43 UTC 2024 - 70.7K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/flatbuffer_export.cc
return tflite::TensorType_UINT16; } else { return Status(absl::StatusCode::kInvalidArgument, "'isSigned' can only be set for 8/16-bits integer type"); } } if (type.isF32()) { return tflite::TensorType_FLOAT32; } else if (type.isF16()) { return tflite::TensorType_FLOAT16; } else if (type.isBF16()) { return tflite::TensorType_BFLOAT16; } else if (type.isF64()) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Jun 12 21:41:49 UTC 2024 - 164.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/ir/tf_ops_a_m.cc
// For f32/f16 data type decision depends on the filter size in spatial // dimensions, for other data types we keep current data format. if (!input_ty.getElementType().isF32() && !input_ty.getElementType().isF16()) return getDataFormat(); // Keep current data format if filter rank is unknown or not equal to 4. auto filter_ty = mlir::dyn_cast<RankedTensorType>(getFilter().getType());
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 146.7K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/stablehlo/transforms/legalize_hlo.cc
return op.emitOpError() << "Missing " << attr_name << " attribute in backend_config"; } auto attr = backend_config.getAs<FloatAttr>(attr_name); if (!attr || !attr.getType().isF32()) { return op.emitOpError() << attr_name << " attribute in backend_config must be of f32 type"; } return success(); }; auto check_bool_attr =
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 154.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/transforms/lower_tf.td
(TF_ConstOp:$one (GetScalarOfType<1> $num_lower)), (TF_ConstOp:$neg_one (GetScalarOfType<-1> $num_lower)), (GetDimensionSize<-2>:$m $input, (IsI32 $num_lower)), (GetDimensionSize<-1>:$n $input, (IsI32 $num_upper)), (TF_SelectV2Op:$num_lower_or_m (TF_LessOp $num_lower, $zero), $m, $num_lower), (TF_SelectV2Op:$num_upper_or_n (TF_LessOp $num_upper, $zero),
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 04 13:30:42 UTC 2024 - 24.7K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/obj9.go
switch { case isS32 && p.From.Offset&0xFFFF == 0 && p.From.Offset != 0: p.As = AADDIS p.From.Offset >>= 16 p.Reg = REG_R0 case isU32 && p.From.Offset&0xFFFF == 0 && p.From.Offset != 0: p.As = AORIS p.From.Offset >>= 16 p.Reg = REG_R0 case isS32 || isU32 || isS34: // The assembler can generate this opcode in 1 (on Power10) or 2 opcodes.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 40.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/tf2xla/transforms/legalize_tf.cc
Eigen::NumTraits<Eigen::bfloat16>::epsilon()); auto value = APFloat(APFloat::BFloat(), APInt(16, raw_epsilon)); return DenseElementsAttr::get(scalar_ty, value); } else if (element_ty.isF32()) { auto value = APFloat(std::numeric_limits<float>::epsilon()); return DenseElementsAttr::get(scalar_ty, value); } else if (element_ty.isF64()) { auto value = APFloat(std::numeric_limits<double>::epsilon());
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 11 20:00:43 UTC 2024 - 291.8K bytes - Viewed (0)