- Sort Score
- Result 10 results
- Languages All
Results 1 - 10 of 10 for RLWINM (0.17 sec)
-
test/codegen/shift.go
// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI" f := tab[byte(v)^b] // ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI" f += tab[byte(v)&b] // ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI" f += tab[byte(v)|b] // ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI" f += tab[uint16(v)&h] // ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI" f += tab[uint16(v)^h]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 21 18:53:43 UTC 2024 - 12.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules
(RLDICL [em] x:(SRDconst [s] a)) && (em&0xFF0000) == 0 => (RLDICL [mergePPC64RLDICLandSRDconst(em, s)] a) // Convert rotated 32 bit masks on 32 bit values into rlwinm. In general, this leaves the upper 32 bits in an undefined state. (AND <t> x:(MOVDconst [m]) n) && t.Size() == 4 && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(0,m,32)] n) // When PCRel is supported, paddi can add a 34b signed constant in one instruction.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 3.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(MOVBZreg (SRWconst x [s])) && mergePPC64AndSrwi(0xFF,s) != 0 => (RLWINM [mergePPC64AndSrwi(0xFF,s)] x) (MOVBZreg (RLWINM [r] y)) && mergePPC64AndRlwinm(0xFF,r) != 0 => (RLWINM [mergePPC64AndRlwinm(0xFF,r)] y) (MOVHZreg (RLWINM [r] y)) && mergePPC64AndRlwinm(0xFFFF,r) != 0 => (RLWINM [mergePPC64AndRlwinm(0xFFFF,r)] y) (MOVWZreg (RLWINM [r] y)) && mergePPC64MovwzregRlwinm(r) != 0 => (RLWINM [mergePPC64MovwzregRlwinm(r)] y)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewrite.go
// Combine (ANDconst [m] (SRWconst [s])) into (RLWINM [y]) or return 0 func mergePPC64AndSrwi(m, s int64) int64 { mask := mergePPC64RShiftMask(m, s, 32) if !isPPC64WordRotateMask(mask) { return 0 } return encodePPC64RotateMask((32-s)&31, mask, 32) } // Test if a word shift right feeding into a CLRLSLDI can be merged into RLWINM. // Return the encoded RLWINM constant, or 0 if they cannot be merged.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 64.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
} x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = int64ToAuxInt(c & 0xFFFFFFFF) v.AddArg(x) return true } // match: (ANDconst [m] (RLWINM [r] y)) // cond: mergePPC64AndRlwinm(uint32(m),r) != 0 // result: (RLWINM [mergePPC64AndRlwinm(uint32(m),r)] y) for { m := auxIntToInt64(v.AuxInt) if v_0.Op != OpPPC64RLWINM { break } r := auxIntToInt64(v_0.AuxInt)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64latelower.go
v.AddArg(n) return true } break } // match: (AND <t> x:(MOVDconst [m]) n) // cond: t.Size() == 4 && isPPC64WordRotateMask(m) // result: (RLWINM [encodePPC64RotateMask(0,m,32)] n) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if x.Op != OpPPC64MOVDconst { continue }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 16.5K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9.go
// clrlslwi ra,rs,b,n -> rlwinm ra,rs,n,b-n,31-n // It maps onto rlwinm which is directly generated here. if n > v || v >= 32 { c.ctxt.Diag("Invalid n or b for CLRLSLWI: %x %x\n%v", v, n, p) } o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.Reg), uint32(n), uint32(v-n), uint32(31-n)) case 63: /* rlwimi/rlwnm/rlwinm [$sh,b],s,[$mask or mb,me],a*/ var mb, me uint32
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0) -
src/cmd/compile/internal/ppc64/ssa.go
p = s.Prog(obj.ANOP) pbover.To.SetTarget(p) case ssa.OpPPC64CLRLSLWI: r := v.Reg() r1 := v.Args[0].Reg() shifts := v.AuxInt p := s.Prog(v.Op.Asm()) // clrlslwi ra,rs,mb,sh will become rlwinm ra,rs,sh,mb-sh,31-sh as described in ISA p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: ssa.GetPPC64Shiftmb(shifts)} p.AddRestSourceConst(ssa.GetPPC64Shiftsh(shifts)) p.Reg = r1 p.To.Type = obj.TYPE_REG
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 55.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLWINM", auxType: auxInt64, argLen: 1, asm: ppc64.ARLWNM, reg: regInfo{ inputs: []inputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)