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Results 51 - 60 of 168 for conv_2d (0.48 sec)
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tensorflow/compiler/mlir/lite/quantization/lite/quantize_model_test.cc
const auto& subgraph = model_.subgraphs[0]; auto conv_op = subgraph->operators[0].get(); const int input_tensor_idx = 0; const int weights_tensor_idx = 1; const int bias_tensor_index = 2; const int output_tensor_idx = 0; const auto bias_tensor = subgraph->tensors[conv_op->inputs[bias_tensor_index]].get(); const auto input_tensor = subgraph->tensors[conv_op->inputs[input_tensor_idx]].get();
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Jun 12 23:15:24 UTC 2024 - 73.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/end2end/conv_2d_nchw.pbtxt
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Dec 03 03:26:13 UTC 2021 - 3.7K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_to_nhwc.mlir
%11 = "tf.Conv2D"(%8, %arg4) { data_format = "NCHW", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "VALID", strides = [1, 1, 1, 1] } : (tensor<?x64x56x56xf32>, tensor<1x1x64x256xf32>) -> tensor<?x256x56x56xf32> // CHECK: %[[CONV2:[0-9]*]] = "tf.Conv2D"(%[[MAX_POOL]], %arg4) // CHECK-SAME: data_format = "NHWC"
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 7.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/tests/lift_quantizable_spots_as_functions.mlir
%0 = "tf.Conv2D"(%arg0, %arg1) { data_format = "NHWC", device = "", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "SAME", strides = [1, 1, 2, 1], use_cudnn_on_gpu = true } : (tensor<1x3x4x3xf32>, tensor<2x3x3x2xf32>) -> tensor<*xf32> %1 = "tf.Relu6"(%0) {device = ""} : (tensor<*xf32>) -> tensor<*xf32> %3 = "tf.Conv2D"(%arg0, %arg1) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri May 10 04:07:09 UTC 2024 - 26.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/tests/insert_quantized_functions.mlir
// CHECK-NOT: func private @internal_conv2d_fn // CHECK-NOT: func private @internal_matmul_fn // CHECK: func private @quantized_conv2d_with_bias_fn // CHECK-SAME: tf_quant.quantized_ops = ["Conv2D", "BiasAdd"] // CHECK: func private @quantized_conv2d_with_bias_and_relu_fn // CHECK: func private @quantized_conv2d_with_bias_and_relu6_fn // CHECK: func private @quantized_conv2d_fn
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Aug 29 01:13:58 UTC 2023 - 3.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/experimental/tac/transforms/device_transform_patterns.h
PatternRewriter& rewriter) const override; }; // Ensure bias for conv2d op. struct EnsureBiasForConv2d : public OpRewritePattern<TFL::Conv2DOp> { using OpRewritePattern<TFL::Conv2DOp>::OpRewritePattern; LogicalResult matchAndRewrite(TFL::Conv2DOp conv_op, PatternRewriter& rewriter) const override; }; // Pad slice to 4d.
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Mar 03 16:37:16 UTC 2022 - 4.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/tests/lift_quantizable_spots_as_functions_drq.mlir
%cst = "tf.Const"() {value = dense<0.000000e+00> : tensor<2xf32>} : () -> tensor<2xf32> %cst_1 = "tf.Const"() {value = dense<3.000000e+00> : tensor<2x3x3x2xf32>} : () -> tensor<2x3x3x2xf32> %0 = "tf.Conv2D"(%arg0, %cst_1) { data_format = "NHWC", device = "", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "SAME", strides = [1, 1, 2, 1], use_cudnn_on_gpu = true
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 11.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/passes/quantized_function_library_xla_weight_only.mlir
parameters[ {"quantized_ops": ["MatMul"], "internal_func_name": "internal_matmul_fn"}, {"quantized_ops": ["Conv2D"], "internal_func_name": "internal_conv2d_fn"}, {"quantized_ops": ["DepthwiseConv2D"], "internal_func_name": "internal_depthwise_conv2d_fn"}, {"quantized_ops": ["Conv3D"], "internal_func_name": "internal_conv3d_fn"}, {"quantized_ops": ["BatchMatMul"], "internal_func_name": "internal_batch_matmul_fn"} ]
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Mar 03 15:43:38 UTC 2023 - 7K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/passes/lift_quantizable_spots_as_functions.cc
} else if (function_name.contains("conv2d")) { // For Conv2D, the channel dimension must be static to calculate the // feature group count. if (!HasStaticShapeAtDims(call_op->getOperand(0), /*dims=*/3)) { return absl::InternalError( "The channel dimension of Conv2D is required to be static."); } } else if (function_name.contains("conv3d")) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri May 10 04:07:09 UTC 2024 - 16.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/tests/quantize_weights.mlir
// CHECK: %[[CONV_1:.*]] = "tf.Conv2D"(%[[GATHER]], %[[DEQUANTIZED_1]]) <{data_format = "NHWC", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "SAME", strides = [1, 1, 2, 1], use_cudnn_on_gpu = true}> {device = ""} : (tensor<1x3x4x3xf32>, tensor<2x3x3x1024xf32>) -> tensor<1x3x2x1024xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 42K bytes - Viewed (0)