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- Result 10 results
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Results 31 - 40 of 86 for vmov (0.04 sec)
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src/cmd/compile/internal/ssa/_gen/S390X.rules
(MOV(B|BZ)reg e:(MOVWreg x)) && clobberIfDead(e) => (MOV(B|BZ)reg x) (MOV(H|HZ)reg e:(MOVHreg x)) && clobberIfDead(e) => (MOV(H|HZ)reg x) (MOV(H|HZ)reg e:(MOVWreg x)) && clobberIfDead(e) => (MOV(H|HZ)reg x) (MOV(W|WZ)reg e:(MOVWreg x)) && clobberIfDead(e) => (MOV(W|WZ)reg x) // Bypass redundant zero extensions. (MOV(B|BZ)reg e:(MOVBZreg x)) && clobberIfDead(e) => (MOV(B|BZ)reg x) (MOV(B|BZ)reg e:(MOVHZreg x)) && clobberIfDead(e) => (MOV(B|BZ)reg x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0) -
src/cmd/compile/internal/riscv64/ggen.go
// ADD $(off), SP, T0 // ADD $(cnt), T0, T1 // loop: // MOV ZERO, (T0) // ADD $Widthptr, T0 // BNE T0, T1, loop p = pp.Append(p, riscv.AADD, obj.TYPE_CONST, 0, off, obj.TYPE_REG, riscv.REG_T0, 0) p.Reg = riscv.REG_SP p = pp.Append(p, riscv.AADD, obj.TYPE_CONST, 0, cnt, obj.TYPE_REG, riscv.REG_T1, 0) p.Reg = riscv.REG_T0 p = pp.Append(p, riscv.AMOV, obj.TYPE_REG, riscv.REG_ZERO, 0, obj.TYPE_MEM, riscv.REG_T0, 0) loop := p
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 19 15:59:22 UTC 2022 - 1.8K bytes - Viewed (0) -
src/runtime/asm_riscv64.s
// X11 already saved (A1) MOV X12, 6*8(X2) MOV X13, 7*8(X2) MOV X14, 8*8(X2) MOV X15, 9*8(X2) MOV X16, 10*8(X2) MOV X17, 11*8(X2) MOV X18, 12*8(X2) MOV X19, 13*8(X2) MOV X20, 14*8(X2) MOV X21, 15*8(X2) MOV X22, 16*8(X2) MOV X23, 17*8(X2) MOV X24, 18*8(X2) MOV X25, 19*8(X2) MOV X26, 20*8(X2) // X27 is g. MOV X28, 21*8(X2) MOV X29, 22*8(X2) MOV X30, 23*8(X2)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Nov 09 13:57:06 UTC 2023 - 27K bytes - Viewed (0) -
src/runtime/rt0_freebsd_riscv64.s
MOV $0x800000, A0 // stacksize = 8192KB MOV $_rt0_riscv64_freebsd_lib_go(SB), A1 MOV A0, 8(X2) MOV A1, 16(X2) MOV $runtime·newosproc0(SB), T0 JALR RA, T0 restore: // Restore callee-save registers, along with X1 (LR). MOV (8*3)(X2), X1 MOV (8*4)(X2), X8 MOV (8*5)(X2), X9 MOV (8*6)(X2), X18 MOV (8*7)(X2), X19 MOV (8*8)(X2), X20 MOV (8*9)(X2), X21 MOV (8*10)(X2), X22 MOV (8*11)(X2), X23
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Sep 28 03:17:13 UTC 2022 - 2.7K bytes - Viewed (0) -
src/runtime/memmove_riscv64.s
BNEZ X5, f_align f_loop_check: MOV $16, X9 BLT X12, X9, f_loop8_check MOV $32, X9 BLT X12, X9, f_loop16_check MOV $64, X9 BLT X12, X9, f_loop32_check f_loop64: MOV 0(X11), X14 MOV 8(X11), X15 MOV 16(X11), X16 MOV 24(X11), X17 MOV 32(X11), X18 MOV 40(X11), X19 MOV 48(X11), X20 MOV 56(X11), X21 MOV X14, 0(X10) MOV X15, 8(X10) MOV X16, 16(X10) MOV X17, 24(X10) MOV X18, 32(X10)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Nov 09 13:57:06 UTC 2023 - 5.5K bytes - Viewed (0) -
src/internal/runtime/syscall/asm_linux_riscv64.s
// err | A2 | part of A0 TEXT ·Syscall6<ABIInternal>(SB),NOSPLIT,$0-80 MOV A0, A7 MOV A1, A0 MOV A2, A1 MOV A3, A2 MOV A4, A3 MOV A5, A4 MOV A6, A5 ECALL MOV $-4096, T0 BLTU T0, A0, err // r1 already in A0 // r2 already in A1 MOV ZERO, A2 // errno RET err: SUB A0, ZERO, A2 // errno MOV $-1, A0 // r1 MOV ZERO, A1 // r2
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Feb 21 21:28:32 UTC 2024 - 969 bytes - Viewed (0) -
src/runtime/duff_riscv64.s
MOV ZERO, (X25) ADD $8, X25 MOV ZERO, (X25) ADD $8, X25 MOV ZERO, (X25) ADD $8, X25 MOV ZERO, (X25) ADD $8, X25 MOV ZERO, (X25) ADD $8, X25 MOV ZERO, (X25) ADD $8, X25 MOV ZERO, (X25) ADD $8, X25 MOV ZERO, (X25) ADD $8, X25 MOV ZERO, (X25) ADD $8, X25 MOV ZERO, (X25) ADD $8, X25 MOV ZERO, (X25) ADD $8, X25 MOV ZERO, (X25) ADD $8, X25 MOV ZERO, (X25)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 30 01:12:57 UTC 2022 - 11.4K bytes - Viewed (0) -
src/crypto/sha512/sha512block_riscv64.s
MOV (0*8)(X20), X5 MOV (1*8)(X20), X6 MOV (2*8)(X20), X7 MOV (3*8)(X20), X8 ADD X5, X10 // H0 = a + H0 ADD X6, X11 // H1 = b + H1 ADD X7, X12 // H2 = c + H2 ADD X8, X13 // H3 = d + H3 MOV X10, (0*8)(X20) MOV X11, (1*8)(X20) MOV X12, (2*8)(X20) MOV X13, (3*8)(X20) MOV (4*8)(X20), X5 MOV (5*8)(X20), X6 MOV (6*8)(X20), X7 MOV (7*8)(X20), X8
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 9.1K bytes - Viewed (0) -
src/runtime/sys_linux_riscv64.s
finish: MOV 8(X2), T0 // sec MOV 16(X2), T1 // nsec // restore stack MOV S2, X2 MOV 24(X2), T2 MOV T2, m_vdsoPC(S3) MOV 32(X2), T2 MOV T2, m_vdsoSP(S3) // sec is in T0, nsec in T1 // return nsec in T0 MOV $1000000000, T2 MUL T2, T0 ADD T1, T0 MOV T0, ret+0(FP) RET fallback: MOV $8(X2), A1 MOV $SYS_clock_gettime, A7 ECALL MOV 8(X2), T0 // sec
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Nov 09 13:57:06 UTC 2023 - 11.5K bytes - Viewed (0) -
src/runtime/rt0_linux_riscv64.s
nocgo: MOV $0x800000, A0 // stacksize = 8192KB MOV $_rt0_riscv64_linux_lib_go(SB), A1 MOV A0, 8(X2) MOV A1, 16(X2) MOV $runtime·newosproc0(SB), T0 JALR RA, T0 restore: // Restore callee-save registers, along with X1 (LR). MOV (8*3)(X2), X1 MOV (8*4)(X2), X8 MOV (8*5)(X2), X9 MOV (8*6)(X2), X18 MOV (8*7)(X2), X19 MOV (8*8)(X2), X20 MOV (8*9)(X2), X21 MOV (8*10)(X2), X22 MOV (8*11)(X2), X23
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 03 09:23:34 UTC 2021 - 2.6K bytes - Viewed (0)