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Results 21 - 30 of 34 for udivisible8 (0.24 sec)

  1. pkg/registry/core/pod/strategy_test.go

    							},
    						}},
    					},
    				},
    			},
    			wantErr: true,
    		},
    		{
    			name: "a new pod setting init-container with indivisible hugepages values while container with divisible hugepages values",
    			pod: &api.Pod{
    				ObjectMeta: metav1.ObjectMeta{
    					Namespace: "default",
    					Name:      "foo",
    				},
    				Spec: api.PodSpec{
    					RestartPolicy: api.RestartPolicyAlways,
    Registered: Sat Jun 15 01:39:40 UTC 2024
    - Last Modified: Wed Apr 24 18:25:29 UTC 2024
    - 76.2K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/tensorflow/ir/tf_ops_a_m.cc

        if (input_batch != ShapedType::kDynamic &&
            input_batch % (block_size * block_size) != 0) {
          return op.emitOpError()
                 << "requires input batch (dimension 0) to be evenly divisible "
                    "by (block_size * block_size), but got input batch "
                 << input_batch << " and block_size " << block_size;
        }
    
        input_shape.assign(input_type.getShape().begin(),
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Apr 25 16:01:03 UTC 2024
    - 146.7K bytes
    - Viewed (0)
  3. src/runtime/malloc.go

    		}
    	}
    	if pagesPerArena%pagesPerSpanRoot != 0 {
    		print("pagesPerArena (", pagesPerArena, ") is not divisible by pagesPerSpanRoot (", pagesPerSpanRoot, ")\n")
    		throw("bad pagesPerSpanRoot")
    	}
    	if pagesPerArena%pagesPerReclaimerChunk != 0 {
    		print("pagesPerArena (", pagesPerArena, ") is not divisible by pagesPerReclaimerChunk (", pagesPerReclaimerChunk, ")\n")
    		throw("bad pagesPerReclaimerChunk")
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 29 17:58:53 UTC 2024
    - 59.6K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/tests/extract_outside_compilation.mlir

        return
      }
    
      // Test that map_outside_compilation's inputs shapes are divisible by num_cores_per_replica.
      func.func @map_outside_compilation_div_num_cores_per_replica() -> () {
        "tf_device.cluster"() ({
          %0 = "tf.OpA"() : () -> tensor<3xi64>
          // expected-error @+1 {{divisible by num_cores_per_replica}}
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Oct 31 08:59:10 UTC 2023
    - 129.6K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/tf2xla/internal/passes/extract_outside_compilation.cc

      if (in_shape[0] % num_cores_per_replica != 0) {
        return context_op->emitOpError()
               << "A map_outside_compilation op's input and output shapes must be "
                  "divisible by num_cores_per_replica="
               << num_cores_per_replica;
      }
      llvm::SmallVector<int64_t, 4> shape;
      shape.push_back(split_size);
      for (int i = 1; i < in_shape.size(); ++i) {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Apr 30 21:25:12 UTC 2024
    - 68.3K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/tensorflow/transforms/shape_inference.cc

                                << kernel_output_features << ") to be divisible by "
                                << "feature_group_count (value "
                                << feature_group_count_val << ").\n";
      }
      if (input_batch % batch_group_count != 0) {
        return op.emitOpError()
               << "Expected input batch dimension (value " << input_batch
               << " ) to be divisible by batch_group_count (value "
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Jun 08 07:28:49 UTC 2024
    - 134.1K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/tensorflow/tests/tf-ops.mlir

    }
    
    // -----
    
    func.func @testConv2D(%arg0: tensor<256x32x32x3xf32>, %arg1: tensor<3x3x2x16xf32>) -> tensor<256x32x32x16xf32> {
      // expected-error @+1 {{requires the number of input channels to be divisible by the number of filter input channels; found 3 and 2, respectively}}
      %0 = "tf.Conv2D"(%arg0, %arg1) {padding = "SAME", strides = [1, 1, 1, 1]} : (tensor<256x32x32x3xf32>, tensor<3x3x2x16xf32>) -> tensor<256x32x32x16xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 23 14:40:35 UTC 2023
    - 236.4K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/tf2xla/transforms/legalize_tf.cc

        // all spatial dimensions.
        const int64_t filter_channels = GetDimSize(filter_ty, num_spatial_dims);
        // TensorFlow convolution op verifies that the number of input channels is
        // divisible by the number of filter channels.
        // For depthwise convolution the feature_group_count argument would be set
        // to the input feature dimension.
        const int64_t feature_group_count =
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 11 20:00:43 UTC 2024
    - 291.8K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/tensorflow/ir/tf_ops_n_z.cc

      if (op.getNumResults() == 0) return failure();
    
      if (input_dim_size % op.getNumResults() != 0)
        return op.emitOpError("dimension #")
               << *dim_index << " not divisible by the number of result tensors";
    
      return success();
    }
    
    //===----------------------------------------------------------------------===//
    // SplitVOp
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 09 22:07:10 UTC 2024
    - 170.8K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/tensorflow/tests/tpu_rewrite.mlir

        // expected-error@+1 {{incorrect input sharding configuration received. 1-th dimension of the input must be evenly divisible by 4}}
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 22:03:30 UTC 2024
    - 172.9K bytes
    - Viewed (0)
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