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Results 21 - 26 of 26 for ror (0.05 sec)

  1. src/cmd/vendor/golang.org/x/arch/x86/x86asm/gnu.go

    SuffixLoop:
    	for i, a := range inst.Args {
    		if a == nil {
    			break
    		}
    		switch a := a.(type) {
    		case Reg:
    			switch inst.Op {
    			case MOVSX, MOVZX:
    				continue
    
    			case SHL, SHR, RCL, RCR, ROL, ROR, SAR:
    				if i == 1 {
    					// shift count does not tell us operand size
    					continue
    				}
    
    			case CRC32:
    				// The source argument does tell us operand size,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:33 UTC 2023
    - 21.4K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/riscv/obj.go

    		// Rotation instructions are supported natively.
    		return []*instruction{ins}
    	}
    
    	switch ins.as {
    	case AROL, AROLW, AROR, ARORW:
    		// ROL -> OR (SLL x y) (SRL x (NEG y))
    		// ROR -> OR (SRL x y) (SLL x (NEG y))
    		sllOp, srlOp := ASLL, ASRL
    		if ins.as == AROLW || ins.as == ARORW {
    			sllOp, srlOp = ASLLW, ASRLW
    		}
    		shift1, shift2 := sllOp, srlOp
    		if ins.as == AROR || ins.as == ARORW {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 77K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    (RotateLeft16 <t> x y) => (RORW <t> (ORshiftLL <typ.UInt32> (ZeroExt16to32 x) (ZeroExt16to32 x) [16]) (NEG <typ.Int64> y))
    (RotateLeft32 x y) => (RORW x (NEG <y.Type> y))
    (RotateLeft64 x y) => (ROR x (NEG <y.Type> y))
    
    (Ctz(64|32|16|8)NonZero ...) => (Ctz(64|32|32|32) ...)
    
    (Ctz64 <t> x) => (CLZ  (RBIT  <t> x))
    (Ctz32 <t> x) => (CLZW (RBITW <t> x))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/rewriteRISCV64.go

    		}
    		val := auxIntToInt64(v_1.AuxInt)
    		v.reset(OpRISCV64RORI)
    		v.AuxInt = int64ToAuxInt(int64(int8(-val) & 63))
    		v.AddArg(x)
    		return true
    	}
    	// match: (ROL x (NEG y))
    	// result: (ROR x y)
    	for {
    		x := v_0
    		if v_1.Op != OpRISCV64NEG {
    			break
    		}
    		y := v_1.Args[0]
    		v.reset(OpRISCV64ROR)
    		v.AddArg2(x, y)
    		return true
    	}
    	return false
    }
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 205.1K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/rewriteARM64.go

    		}
    		p := v_0.Args[0]
    		v.copyOf(p)
    		return true
    	}
    	return false
    }
    func rewriteValueARM64_OpARM64ROR(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (ROR x (MOVDconst [c]))
    	// result: (RORconst x [c&63])
    	for {
    		x := v_0
    		if v_1.Op != OpARM64MOVDconst {
    			break
    		}
    		c := auxIntToInt64(v_1.AuxInt)
    		v.reset(OpARM64RORconst)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 608.6K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/opGen.go

    			},
    			outputs: []outputInfo{
    				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
    			},
    		},
    	},
    	{
    		name:   "ROR",
    		argLen: 2,
    		asm:    arm64.AROR,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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