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Results 11 - 20 of 29 for MOVHreg (0.44 sec)
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src/cmd/compile/internal/ssa/rewriteRISCV64latelower.go
v.AuxInt = int64ToAuxInt(56 + c) v0 := b.NewValue0(v.Pos, OpRISCV64SLLI, typ.Int64) v0.AuxInt = int64ToAuxInt(56) v0.AddArg(x) v.AddArg(v0) return true } // match: (SRAI [c] (MOVHreg x)) // cond: c < 16 // result: (SRAI [48+c] (SLLI <typ.Int64> [48] x)) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpRISCV64MOVHreg { break } x := v_0.Args[0] if !(c < 16) {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Jan 19 22:42:34 UTC 2023 - 5.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteS390X.go
typ := &b.Func.Config.Types // match: (MOVHreg e:(MOVBreg x)) // cond: clobberIfDead(e) // result: (MOVBreg x) for { e := v_0 if e.Op != OpS390XMOVBreg { break } x := e.Args[0] if !(clobberIfDead(e)) { break } v.reset(OpS390XMOVBreg) v.AddArg(x) return true } // match: (MOVHreg e:(MOVHreg x)) // cond: clobberIfDead(e)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 395.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
(MOVBreg (ANDconst [c] x)) && c & 0x80 == 0 => (ANDconst [c&0x7f] x) (MOVHreg (ANDconst [c] x)) && c & 0x8000 == 0 => (ANDconst [c&0x7fff] x) // fold double extensions (MOVBreg x:(MOVBreg _)) => (MOVWreg x) (MOVBUreg x:(MOVBUreg _)) => (MOVWreg x) (MOVHreg x:(MOVBreg _)) => (MOVWreg x) (MOVHreg x:(MOVBUreg _)) => (MOVWreg x) (MOVHreg x:(MOVHreg _)) => (MOVWreg x) (MOVHUreg x:(MOVBUreg _)) => (MOVWreg x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteMIPS.go
} v.reset(OpMIPSMOVWreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUreg _)) // result: (MOVWreg x) for { x := v_0 if x.Op != OpMIPSMOVBUreg { break } v.reset(OpMIPSMOVWreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHreg _)) // result: (MOVWreg x) for { x := v_0 if x.Op != OpMIPSMOVHreg { break }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 176.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteLOONG64.go
} v.reset(OpLOONG64MOVVreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUreg _)) // result: (MOVVreg x) for { x := v_0 if x.Op != OpLOONG64MOVBUreg { break } v.reset(OpLOONG64MOVVreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHreg _)) // result: (MOVVreg x) for { x := v_0 if x.Op != OpLOONG64MOVHreg {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 195.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteRISCV64.go
} v.reset(OpRISCV64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpRISCV64MOVBUreg { break } v.reset(OpRISCV64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpRISCV64MOVHreg {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 205.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteMIPS64.go
} v.reset(OpMIPS64MOVVreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUreg _)) // result: (MOVVreg x) for { x := v_0 if x.Op != OpMIPS64MOVBUreg { break } v.reset(OpMIPS64MOVVreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHreg _)) // result: (MOVVreg x) for { x := v_0 if x.Op != OpMIPS64MOVHreg { break
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 31 03:59:48 UTC 2023 - 211.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPSOps.go
{name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"}, // move from arg0, sign-extended from byte {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH"}, // move from arg0, sign-extended from half {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
{name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"}, // move from arg0, sign-extended from byte {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH"}, // move from arg0, sign-extended from half {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:19 UTC 2023 - 25.2K bytes - Viewed (0)