- Sort Score
- Result 10 results
- Languages All
Results 1 - 4 of 4 for AMIN (0.06 sec)
-
src/cmd/internal/obj/riscv/cpu.go
ASH2ADDUW ASH3ADD ASH3ADDUW ASLLIUW // 1.2: Basic Bit Manipulation (Zbb) AANDN AORN AXNOR ACLZ ACLZW ACTZ ACTZW ACPOP ACPOPW AMAX AMAXU AMIN AMINU ASEXTB ASEXTH AZEXTH // 1.3: Bitwise Rotation (Zbb) AROL AROLW AROR ARORI ARORIW ARORW AORCB AREV8 // 1.5: Single-bit Instructions (Zbs)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/inst.go
return &inst{0x3, 0x2, 0x0, 0, 0x0} case ALWU: return &inst{0x3, 0x6, 0x0, 0, 0x0} case AMAX: return &inst{0x33, 0x6, 0x0, 160, 0x5} case AMAXU: return &inst{0x33, 0x7, 0x0, 160, 0x5} case AMIN: return &inst{0x33, 0x4, 0x0, 160, 0x5} case AMINU: return &inst{0x33, 0x5, 0x0, 160, 0x5} case AMRET: return &inst{0x73, 0x0, 0x2, 770, 0x18} case AMUL: return &inst{0x33, 0x0, 0x0, 32, 0x1}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.9K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
AMUL, AMULH, AMULHU, AMULHSU, AMULW, ADIV, ADIVU, ADIVW, ADIVUW, AREM, AREMU, AREMW, AREMUW, AADDUW, ASH1ADD, ASH1ADDUW, ASH2ADD, ASH2ADDUW, ASH3ADD, ASH3ADDUW, ASLLIUW, AANDN, AORN, AXNOR, AMAX, AMAXU, AMIN, AMINU, AROL, AROLW, AROR, ARORW, ARORI, ARORIW, ABCLR, ABCLRI, ABEXT, ABEXTI, ABINV, ABINVI, ABSET, ABSETI: p.Reg = p.To.Reg } } // Rewrite instructions with constant operands to refer to the immediate
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0) -
RELEASE.md
## Thanks to our Contributors This release contains contributions from many people at Google, as well as:
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 11 23:24:08 UTC 2024 - 730.3K bytes - Viewed (0)