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Results 51 - 60 of 75 for sdiv (0.07 sec)

  1. tensorflow/compiler/mlir/lite/transforms/optimize_patterns.td

    def ExpandTo4DForDepthwiseConv: NativeCodeCall<
      "ExpandTo4DForDepthwiseConv($0)">;
    
    // If we see a (div or Mul) op (dividing/multiplying) a constant value
    // to a convolution op with constant filter and bias, we can fuse the div/mul
    // into the convolution op by constant folding
    // the filter/bias and the div/mul op's constant operand.
    // The following pattern restricts to float constant values for now.
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 16 20:31:41 UTC 2024
    - 66.4K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/lite/tests/legalize-tf.mlir

    // CHECK:  "tfl.zeros_like"(%arg0) : (tensor<8x16xf32>) -> tensor<8x16xf32>
    }
    
    func.func @div(%arg0: tensor<1xf32>, %arg1: tensor<1xf32>) -> tensor<1xf32> {
      %0 = "tf.Div"(%arg0, %arg1) : (tensor<1xf32>, tensor<1xf32>) -> tensor<1xf32>
      func.return %0: tensor<1xf32>
    
    // CHECK-LABEL: div
    // CHECK:  tfl.div %arg0, %arg1 {fused_activation_function = "NONE"} : tensor<1xf32>
    // CHECK:  return
    }
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Jun 05 01:54:33 UTC 2024
    - 153.4K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/lite/stablehlo/tests/legalize_hlo.mlir

      func.return %0 : tensor<4x4x4x4xi32>
    }
    
    // CHECK-LABEL:   func @div(
    // CHECK-SAME:              %[[VAL_0:.*]]: tensor<2xi32>) -> tensor<2xi32> {
    // CHECK:           %[[VAL_1:.*]] = "tf.Div"(%[[VAL_0]], %[[VAL_0]]) : (tensor<2xi32>, tensor<2xi32>) -> tensor<2xi32>
    // CHECK:           return %[[VAL_1]] : tensor<2xi32>
    // CHECK:         }
    func.func @div(%arg0: tensor<2xi32>) -> tensor<2xi32> {
      %0 = mhlo.divide %arg0, %arg0 : tensor<2xi32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed May 29 07:26:59 UTC 2024
    - 340.2K bytes
    - Viewed (0)
  4. platforms/documentation/docs/src/docs/css/base.css

        border-radius: 1px;
    }
    
    .hamburger__bar + .hamburger__bar {
        margin-top: 4px;
    }
    
    .site-header {
        background-color: white;
    }
    
    /* Override javadoc styles */
    .site-header div {
        font-family: 'Lato', Arial, sans-serif;
    }
    
    .site-header__navigation-header a {
        align-self: center;
        border-bottom: 0 none;
        height: 36px;
    }
    
    .site-header .site-header-version {
    Registered: Wed Jun 12 18:38:38 UTC 2024
    - Last Modified: Sat May 25 05:15:02 UTC 2024
    - 30.5K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/tensorflow/ir/tf_generated_ops.td

      );
    
      let results = (outs);
    }
    
    def TF_DivOp : TF_Op<"Div", [Pure, ResultsBroadcastableShape, TF_SameOperandsAndResultElementTypeResolveRef]>,
                   WithBroadcastableBinOpBuilder {
      let summary = "Returns x / y element-wise.";
    
      let description = [{
    *NOTE*: `Div` supports broadcasting. More about broadcasting
    [here](http://docs.scipy.org/doc/numpy/user/basics.broadcasting.html)
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 11 23:24:08 UTC 2024
    - 793K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssagen/ssa.go

    	{ir.ODIV, types.TFLOAT32}: ssa.OpDiv32F,
    	{ir.ODIV, types.TFLOAT64}: ssa.OpDiv64F,
    
    	{ir.ODIV, types.TINT8}:   ssa.OpDiv8,
    	{ir.ODIV, types.TUINT8}:  ssa.OpDiv8u,
    	{ir.ODIV, types.TINT16}:  ssa.OpDiv16,
    	{ir.ODIV, types.TUINT16}: ssa.OpDiv16u,
    	{ir.ODIV, types.TINT32}:  ssa.OpDiv32,
    	{ir.ODIV, types.TUINT32}: ssa.OpDiv32u,
    	{ir.ODIV, types.TINT64}:  ssa.OpDiv64,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jun 10 19:44:43 UTC 2024
    - 284.9K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/asm/testdata/ppc64.s

    	FMULCC F1, F2, F3               // fc620073
    	FMULS F1, F2                    // ec420072
    	FMULS F1, F2, F3                // ec620072
    	FMULSCC F1, F2, F3              // ec620073
    	FDIV F1, F2                     // fc420824
    	FDIV F1, F2, F3                 // fc620824
    	FDIVCC F1, F2, F3               // fc620825
    	FDIVS F1, F2                    // ec420824
    	FDIVS F1, F2, F3                // ec620824
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
  8. samples/bookinfo/src/productpage/static/tailwind/tailwind.css

    ngth);if(n||a){e.remove();return}e.value=r}parse(e){let t=zm(e),r=[],n=[];for(let a of t.nodes)n.push(a),a.type==="div"&&a.value===","&&(r.push(n),n=[]);return r.push(n),r.filter(a=>a.length>0)}stringify(e){if(e.length===0)return"";let t=[];for(let r of e)r[r.length-1].type!=="div"&&r.push(this.div(e)),t=t.concat(r);return t[0].type==="div"&&(t=t.slice(1)),t[t.length-1].type==="div"&&(t=t.slice(0,-2+1||void 0)),zm.stringify({nodes:t})}clone(e,t,r){let n=[],a=!1;for(let s of r)!a&&s.type==="word"...
    Registered: Fri Jun 14 15:00:06 UTC 2024
    - Last Modified: Tue May 28 14:48:01 UTC 2024
    - 357.1K bytes
    - Viewed (1)
  9. src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

    		{name: "POPCNTB", argLength: 1, reg: gp11, asm: "POPCNTB"}, // number of set bits in each byte of arg0 placed in corresponding byte
    
    		{name: "FDIV", argLength: 2, reg: fp21, asm: "FDIV"},   // arg0/arg1
    		{name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS"}, // arg0/arg1
    
    		{name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", typ: "Int64"},   // arg0/arg1 (signed 64-bit)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 43.8K bytes
    - Viewed (0)
  10. analysis/analysis-api-fe10/src/org/jetbrains/kotlin/analysis/api/descriptors/components/KaFe10Resolver.kt

            private val operatorWithAssignmentVariant = setOf(
                OperatorNameConventions.PLUS,
                OperatorNameConventions.MINUS,
                OperatorNameConventions.TIMES,
                OperatorNameConventions.DIV,
                OperatorNameConventions.REM,
                OperatorNameConventions.MOD,
            )
    
            private val callArgErrors = setOf(
                Errors.ARGUMENT_PASSED_TWICE,
    Registered: Wed Jun 12 09:53:16 UTC 2024
    - Last Modified: Tue Jun 11 15:45:42 UTC 2024
    - 38.5K bytes
    - Viewed (0)
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